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14 

Table 3-1. Master Transmit Status Codes 

Code 

I

2

C State 

Microprocessor Response 

Next I

2

C Action 

18h 

Addr + W transmitted, 
ACK received 

7-bit address:  
Write byte to DATA, clear IFLG 
 

OR 

 
Set STA, clear IFLG 
 

OR 

 
Set STP, clear IFLG 
 

OR 

 
Set STA & STP, clear IFLG 
 
10-bit address:  
Write extended address byte to 
DATA, clear IFLG 

 
Transmit data byte, receive 
ACK 
 
 
Transmit repeated START 
 
 
 
Transmit STOP 
 
 
 
Transmit STOP, then START 
 
 
Transmit extended address byte 

20h 

Addr + W transmitted, 
ACK not received 

Same as code 18h 

Same as code 18h 

38h 

Arbitration lost 

Clear IFLG 
 

OR 

 
Set STA, clearIFLG 

Return to idle 
 
 
 
Transmit START when bus is free 

68h 

Arbitration lost, 
SLA + W received, 
ACK transmitted 

Clear IFLG, AAK=0 
 

OR 

 
Clear IFLG, AAK=1 

Receive data byte, transmit not ACK 
 
 
 
Receive data byte, transmit ACK 

78h Arbitration 

lost, 

general call addr 
received, ACK 
transmitted 

Same as code 68h 

Same as code 68h 

B0h 

Arbitration lost, SLA + R 
received, ACK 
transmitted 

Write byte to DATA, clear IFLG, 
AAK=0 
 

OR 

 
Write byte to DATA, clear IFLG, 
AAK=1 

Transmit last byte, receive ACK 
 
 
 
 
Transmit data byte, receive ACK 

 

Summary of Contents for DSTni DSTni-EX

Page 1: ...Part Number 900 335 Revision A 3 04 DSTni EX User Guide Section Five ...

Page 2: ......

Page 3: ...PI is a trademark of Motorola Inc No part of this guide may be reproduced or transmitted in any form for any purpose other than the purchaser s personal use without the express written permission of Lantronix Inc Lantronix 15353 Barranca Parkway Irvine CA 92618 USA Phone 949 453 3990 Fax 949 453 3995 Technical Support Phone 630 245 1445 Fax 630 245 1717 Master Distributor Grid Connect 1841 Centre ...

Page 4: ...Lantronix will ship the replacement media to the customer In no event will Lantronix be responsible to the user in contract in tort including negligence strict liability or otherwise for any special indirect incidental or consequential damage or loss of equipment plant or power system cost of capital loss of profits or revenues cost of replacement power additional expenses in the use of existing s...

Page 5: ..._______________________________________________________ 13 Operating Modes _________________________________________________________ 13 Bus Clock Considerations __________________________________________________ 21 Programmer s Reference_____________________________________________________ 22 I 2 C Controller Register Summary_______________________________________________ 22 I 2 C Controller Regis...

Page 6: ...________________________________________ 72 Interrupt Enable Registers__________________________________________________ 73 CAN Operating Mode _____________________________________________________ 74 CAN Configuration Registers _______________________________________________ 75 Acceptance Filter and Acceptance Code Mask__________________________________ 78 CANbus Analysis__________________________...

Page 7: ...trol Register Definitions 49 Table 4 23 Endpoint Control Register Definitions 50 Table 5 1 Bit Rates for Different Cable Lengths 57 Table 5 2 CAN I O Address 58 Table 5 3 CAN Channel Register Summary 58 Table 5 4 Detailed CAN Register Map 60 Table 5 5 TxMessage_0 ID28 64 Table 5 6 TxMessage_0 ID12 64 Table 5 7 TxMessage_0 Data 55 64 Table 5 8 TxMessage_0 Data 39 64 Table 5 9 TxMessage_0 Data 23 64...

Page 8: ...ance Code Register 80 Table 5 55 Acceptance Code Register Definitions 80 Table 5 56 Acceptance Mask Register ID12 80 Table 5 57 Acceptance Mask Register ID12 Definitions 80 Table 5 58 Acceptance Mask Register Data 55 80 Table 5 59 Acceptance Mask Register Data 55 Definitions 80 Table 5 60 Arbitration Lost Capture Register 81 Table 5 61 Arbitration Lost Capture Register Definitions 81 Table 5 62 Er...

Page 9: ...ution on a single chip enables system designers to build affordable full function solutions that provide the highest level of performance in both processing power and peripheral systems while reducing the number of total system components The advantages gained from this synergy include Simplifying system design and increased reliability Minimizing marketing and administration costs by eliminating ...

Page 10: ...owing conventions to alert you to information of special interest The symbols and n are used throughout this Guide to denote active LOW signals Notes Notes are information requiring attention Navigating Online The electronic Portable Document Format PDF version of this User Guide contains hyperlinks Clicking one of these hyper links moves you to that location in this User Guide The PDF file was cr...

Page 11: ...Tni timers Section 4 Ethernet Controllers Describes the DSTni Ethernet controllers Section 4 Ethernet PHY Describes the DSTni Ethernet physical layer core Section 5 SPI Controller Describes the DSTni Serial Peripheral Interface SPI controller Section 5 I2C Controller Describes the DSTni I2 C controller Section 5 USB Controller Describes the DSTni USB controller Section 5 CAN Controllers Describes ...

Page 12: ...evices have an 8 bit shift register for a combined register of 16 bits During an SPI transfer the master and slave shift registers by eight bits and exchange their 8 bit register values starting with the most significant bit The SPI interface is software configurable The clock polarity clock phase SLVSEL polarity clock frequency in master mode and number of bits to be transferred are all software ...

Page 13: ...result to generate SCLK The SPI interface includes the internal interrupt connection SPI interrupt In SPI master mode an SPI interrupt occurs when the Transmit Holding register is empty In SPI slave mode an SPI interrupt occurs when the SLVSEL pin transitions from active to inactive A familiar Interrupt Control register is provided for the SPI interrupt The interrupt has a two CPU clock delay from...

Page 14: ...2 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET B800 FIELD DATA 7 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW R W RW RW RW RW RW RW RW RW RW RW RW RW RW Table 2 3 SPI_DATA Register Definitions Bits Field Name Description 15 8 Reserved Always returns zero 7 0 DATA 7 0 Data The location where the CPU reads data from or writes data for the SPI interface ...

Page 15: ...the data register 0 disabled default 5 INVCS Invert Chip Select 1 inverted CS 0 normal default 4 PHASE Phase Select Selects the operating mode for the SPI interface The two modes select where the opposite edge D Flip Flop is placed 1 the negative edge flop is inserted into the shift_out path to hold the data for an extra clock 0 a negative edge flop is inserted into the shift_in path default 3 CKP...

Page 16: ...aster mode transfer or that SLVSEL_N input has not gone HIGH on a slave transfer default It takes two CPU clocks after SLVSEL_n changes to see the interrupt 6 OVERRUN Overrun 1 SPIDAT register is written to while an SPI transfer is in progress or SLVSEL_N goes active in master mode 0 SPIDAT register has not been written to or SLVSEL_N has not gone active in master mode default 5 COL Collision 1 a ...

Page 17: ...ols the number of bits shifted between the master and slave device during a transfer when this device is the master See Table 2 10 5 1 Reserved Always returns zero 0 SELECTO SelectO Signal This bit is the select output for master mode 1 this bit drives the SLVSEL pin active 0 this bit inactivates SLVSEL default This bit is not used with Autodrv If using Autodrv leave this bit set to 0 The INVCS is...

Page 18: ... rate during master mode DVD_CNTR_HI and this byte generate a 16 bit divisor that generates the SPI clock DVD_CNTR_HI DVD_CNTR_HI is the DVD Counter High Byte register Table 2 13 DVD_CNTR_HI Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET B80A FIELD DVDCNT 15 8 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 2 14 DVD_CNTR_HI Register Definit...

Page 19: ...2 C Controller Register Definitions on page 23 Features Master or slave operation Multmaster operation Software selectable acknowledge bit Arbitration lost interrupt with automatic mode switching from master to slave Calling address identification interrupt with automatic mode switching from master to slave START and STOP signal generation detection Repeated START signal generation Acknowledge bit...

Page 20: ... maximum bus capacitance of 400 pF Both the SDA and SCL lines are bidirectional connected to a positive supply voltage via a pull up resistor When the bus is free both lines are HIGH The output stages of devices connected to the bus must have an open drain or open collector to perform the wired AND function Each device on the bus has a unique address and can operate as either a transmitter or rece...

Page 21: ...o one The following actions occur 1 The DATA register loads either a 7 bit slave address or the first part of a 10 bit slave address with the least significant bits cleared to zero to specify transmit mode 2 The M I2 C tests the I2 C bus and sends a START condition when the bus is free 3 The IFLG bit is set and the status code in the Status register becomes 08h 4 The IFLG bit clears to zero to pro...

Page 22: ...dress byte 20h Addr W transmitted ACK not received Same as code 18h Same as code 18h 38h Arbitration lost Clear IFLG OR Set STA clearIFLG Return to idle Transmit START when bus is free 68h Arbitration lost SLA W received ACK transmitted Clear IFLG AAK 0 OR Clear IFLG AAK 1 Receive data byte transmit not ACK Receive data byte transmit ACK 78h Arbitration lost general call addr received ACK transmit...

Page 23: ...rbitration lost SLA W received ACK transmitted Clear IFLG AAK 0 OR Clear IFLG AAK 1 Receive data byte transmit not ACK Receive data byte transmit ACK B0h Arbitration lost SLA R received ACK transmitted Write byte to DATA Clear IFLG AAK 0 OR Write byte to DATA Clear IFLG AAK 1 Transmit data byte receive ACK Transmit data byte receive ACK D0h Second Address byte W transmitted ACK received Write byte...

Page 24: ...1 to this bit in the Control register The I2 C controller Transmits a STOP condition Clears the STP bit Returns to the idle state Master Receive Mode In master receive mode the I2 C controller receives a number of bytes from a slave transmitter After the START condition transmits 1 The IFLG bit is set and status code 08h is in the Status register 2 The Data register has the slave address or the fi...

Page 25: ...Write extended address byte to DATA clear IFLG Transmit repeated START Transmit STOP Transmit STOP and START Transmit extended address byte 38h Arbitration lost Clear IFLG OR Set STA clearIFLG Return to idle Transmit START when bus is free 68h Arbitration lost SLA W received ACK transmitted Clear IFLG AAK 0 OR Clear IFLG AAK 1 Receive data byte transmit not ACK Receive data byte transmit ACK 78h A...

Page 26: ...1 Receive data byte transmit not ACK Receive data byte transmit ACK 78h Arbitration lost SLA R received ACK transmitted Write byte to DATA Clear IFLG AAK 0 OR Write byte to DATA Clear IFLG AAK 1 Transmit data byte receive ACK Transmit data byte receive ACK B0h Arbitration lost Clear IFLG OR Set STA clear IFLG Return to idle Transmit START when bus free E0h Second Address byte R transmitted ACK rec...

Page 27: ...he I2 C controller enters slave transmit mode when it receives its own slave address and a read bit after a START condition The I2 C controller then transmits an acknowledge bit and sets the IFLG bit in the Control register The Status register contains the status code A8h Note If the I2 C controller has an extended slave address signified by F0h F7h in the Slave Address register it transmits an ac...

Page 28: ...e IFLG is not set and the status does not change Only after receiving the second address byte does the I2 C controller generate an interrupt and set the IFLG bit and the status code as described above The I2 C controller also enters slave transmit mode directly from a master mode if arbitration is lost during address transmission and both the slave address and write bit or general call address if ...

Page 29: ...onizes its clock to the I2 C bus clock The device that generates the shortest high clock period determines the high period of the clock The device that generates the longest LOW clock period determines the LOW period of the clock When the I2 C controller is in master mode and is communicating with a slow slave the slave can stretch each bit period by holding the SCL line LOW until it is ready for ...

Page 30: ...buffers with open collector or open drain outputs and Schmitt inputs I2 C Controller Register Summary The A 2 0 address lines of the microprocessor interface provide access to the 8 bit registers in Table 3 7 On a hardware reset Address Extended Slave Address Data and Control register clear to 00h The Status register is set to F8h The Clock Control register is set to 00h On a software reset the ST...

Page 31: ...ler receives this address after a START condition it generates an interrupt and enters slave mode SLA6 corresponds to the first bit received from the I 2 C bus For 10 bit addressing when the address received starts with F0h F7h the I 2 C controller recognizes the correspondence to SLAX9 and SLAX8 of an extended address and sends an ACK The device does not generate an interrupt at this point After ...

Page 32: ...After each byte transmits the Data register contains the byte present on the bus therefore if arbitration is lost the Data register has the correct receive byte Table 3 10 Data Register BIT 7 6 5 4 3 2 1 0 OFFSET D002 FIELD Transmission Data Slave Address or Receipt Data Byte RESET 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW Table 3 11 Data Register Definitions Bits Field Name Description 7 0 SLA6 ...

Page 33: ...I 2 C controller is being accessed in slave mode the I 2 C controller completes the data transfer in slave mode and enters master mode when the bus is released The STA bit is cleared automatically after a START condition has been sent 0 no effect 4 STP Stop Condition 1 and I 2 C controller is in slave mode in master mode a stop condition is transmitted on the I 2 C bus 0 and I 2 C controller is in...

Page 34: ...r can contain any of the 31 status codes in Table 3 16 When this register contains the status code F8h No relevant status information is available No interrupt is generated The IFLG bit in the Control register is not set All other status codes correspond to a defined state of the I2 C controller as described in Table 3 16 When entering each of these states the corresponding status code appears in ...

Page 35: ...eceived ACK sent 70h General Call address received ACK sent 78h Arbitration lost in address as master General Call address received ACK sent 80h Data byte received after slave address received ACK sent 88h Data byte received after slave address received no ACK sent 90h Data byte received after General Call received ACK sent 98h Data byte received after General Call received ACK not sent A0h STOP o...

Page 36: ...F1 10 FOSCL F1 10 CLK 2N M 1 10 Using two separately programmable dividers allows the master mode output frequency to be set independently of the frequency at which the I2 C bus is sampled This is particularly useful in multi master systems because the frequency at which the I2 C bus is sampled must be at least 10 times the frequency of the fastest master on the bus to ensure that START and STOP c...

Page 37: ... SLAX4 Extended slave address 3 SLAX3 Extended slave address 2 SLAX2 Extended slave address 1 SLAX1 Extended slave address 0 SLAX0 Extended slave address Software Reset Register Table 3 21 Software Reset Register BIT 7 6 5 4 3 2 1 0 OFFSET D00E FIELD HRST RESET 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW Table 3 22 Software Reset Register Definitions Bits Field Name Description 7 HRST Hardware Rese...

Page 38: ...SB Register Summary on page 38 USB Register Definitions on page 39 Host Mode Operation on page 50 Sample Host Mode Operations on page 51 USB Pull up Pull down Resistors on page 53 USB Interface Signals on page 54 Features Fully USB 1 1 compliant device 8 bidirectional endpoints DMA or FIFO data stream interface Host mode logic for emulating a PC host Supports embedded host controller ...

Page 39: ... with external interrupt 3 USB Core The USB core has three functional blocks Serial Interface Engine SIE Microprocessor Interface Digital Phase Locked Loop Logic Serial Interface Engine The USB Serial Interface Engine USB SIE has two major sections Tx Logic and Rx Logic Tx Logic formats and transmits data packets that the microprocessor builds in memory These packets are converted from a parallel ...

Page 40: ...B Protocol Layer the CPU handles the higher level USB Device Framework buffer management and peripheral dependent functions The hardware software interface of the USB provides both a slave interface and a master interface The slave interface consists of the Control Registers Block CRB which configure the USB and provide status and interrupts to the microprocessor The master interface is the USB in...

Page 41: ...n system memory The USB has full read and write access and the microprocessor should not modify the BD or its corresponding data buffer The BD also contains indirect address pointers to where the actual buffer resides in system memory Rx vs Tx as a Target Device or Host The USB core can function as either a USB target device function or a USB host and can switch operating modes between host and ta...

Page 42: ...corresponding buffer in system memory To compute the entry point in to the BDT the BDT_PAGE register is concatenated with the current endpoint and the TX and ODD fields to form the following 16 bit address Table 4 2 16 Bit USB Address BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD BDT_PAGE REGISTER END_POINT TX ODD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW R RW RW RW RW RW RW RW RW RW RW RW ...

Page 43: ...etion No address increment FIFO Mode Data Toggle Synchronization enable Amount of data to be transmitted or received Amount of data transmitted or received Where the buffer resides in system memory Where the buffer resides in system memory Table 4 5 shows the USB BD format Table 4 5 USB Buffer Descriptor Format 7 6 5 4 3 2 1 0 OWN DATA0 1 USB_OWN NINC DTS RSVD 0 0 0 BC 7 0 0 BCH9 BCH8 Low Byte ADD...

Page 44: ...ation forcing the DMA engine to read or write from the same address This is useful for endpoints when data must be read from or written to a single location such as a FIFO Typically this bit is set with the USB_OWN bit for ISO endpoints that interface with a FIFO If USB_OWN 1 the USB does not change this bit otherwise the USB writes bit 2 of the current token PID to the BD 3 DTS Data Toggle Synchr...

Page 45: ...ates the BDT and changes the OWN bit to 0 if KEEP is 0 4 The USB updates the STAT register and sets the TOK_DNE interrupt 5 When the microprocessor processes the TOK_DNE interrupt 6 The microprocessor reads the status register for the information it needs to process the endpoint 7 The microprocessor allocates a new BD so the endpoint can transmit or receive additional USB data then processes the l...

Page 46: ...ss that the USB decodes in peripheral mode 45 08 FRM_NUM Contains the 11 bit frame number 46 0A TOKEN Performs USB transactions during host mode Dedicated to host mode 47 0D Reserved 0E Reserved 0F Reserved 10 Reserved 11 ENDPT1 Endpoint control 1 bit 49 12 ENDPT2 Endpoint control 2 bit 49 13 ENDPT3 Endpoint control 3 bit 49 14 ENDPT4 Endpoint control 4 bit 49 15 ENDPT5 Endpoint control 5 bit 49 1...

Page 47: ...ble 4 8 Interrupt Status Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 00h Interrupt Mask Interrupt Status FIELD STALL ATTACH RESUME SLEEP TOK_DNE SOF_TOK ERROR USB_RST STALL ATTACH RESUME SLEEP TOK_DNE SOF_TOK ERROR USB_RST RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 4 9 16 Interrupt Status Register Definitions Bits Field Name Descrip...

Page 48: ...le on the USB bus signals for 3 ms Activity on the USB bus resets the sleep timer 0 USB does not detect constant idle 3 TOK_DNE Token Processing 1 the current token being processed is complete The microprocessor should read the STAT register immediately to determine the endpoint and BD used for this token Clearing this bit by writing a 1 clears the STAT register or loads the STAT holding register ...

Page 49: ...RR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 4 11 16 Error Interrupt Status Register Definitions Bits Field Name Description 15 BITSERR Enable Disable BITSERR Interrupt 1 enable the BITSERR interrupt 0 disable the BITSERR interrupt default 14 Reserved 13 DMAERR Enable Disable DMAERR Interrupt 1 enable the DMAERR interrupt 0 disab...

Page 50: ...shake phases of a IN TOKEN If more that 16 bit times are counted from the previous EOP before a transition from IDLE a bus turnaround time out error occurs 3 DFN8 Data Field Received Not 8 Bits The USB Specification 1 0 states that the data field must be an integral number of bytes If the data field is not an integral number of bytes this bit is set 2 CRC16 CRC16 Failure 1 data packet is rejected ...

Page 51: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 04h Control Status FIELD JSTATE SE0 TXDSUSPEND TOKENBUSY RESET HOSTMODE EN RESUME ODD_RST USB_EN ENDP TX ODD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R Table 4 13 Status Register Definitions Bits Field Name Description 15 JSTATE Live USB Differential Receiver JSTATE Signal The polarity of this signal is effected by the current s...

Page 52: ...e Resume signaling when the RESUME bit is cleared For more information about RESUME signaling see Section 7 1 4 5 of the USB specification version 1 0 0 prevents the USB from executing resume signaling 9 ODD_RST BDT PDD Reset 1 resets all the BDT ODD ping pong bits to 0 which then specifies the EVEN BDT bank 0 does not reset the BDT ODD ping pong bits 8 USB_EN USB Enable 1 enables the USB to opera...

Page 53: ... memory Table 4 14 Address Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 06h BDT Page Register Address Register FIELD BDT_BA 15 8 LS_EN ADDR 6 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R Table 4 15 16 Address Register Definitions Bits Field Name Description 15 8 BDT_BA BDT Base Address This 8 bit value is the most significant bits of the BDT base address ...

Page 54: ... a SOF_TOKEN is received Table 4 16 Frame Number Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 08h FIELD FRM 10 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R Table 4 17 Frame Number Register Definitions Bits Field Name Description 15 11 Reserved 10 0 FRM 10 0 Frame Number The 11 bits of the Frame Number ...

Page 55: ...en host mode is enabled the 14 bit SOF counter counts the interval between SOF frames The SOF must be transmitted every 1us so the SOF counter is loaded with a value of 12000 When the SOF counter reaches zero a Start of Frame SOF token is transmitted The SOF Threshold register programs the number of USB byte times before the SOF to stop initiating token packet transactions This register must be se...

Page 56: ...iption 15 8 CNT 7 0 SOF Count Threshold Represent the SOF count threshold in byte times 7 4 TOKEN_PID Token Type The token type that the SUB executes see Table 4 20 3 0 TOKEN_ENDPT Endpoint for Token Command Determines the endpoint address for the token command The 4 bit value that is written must be for a valid endpoint Table 4 20 Valid PID Tokens Token_PID Token Type Description 0001 OUT Token U...

Page 57: ...send a token to a low speed device This is required to communicate with a low speed device through a hub 6 RETRY_DIS Host Mode Only Bit A host mode only bit that is present only in the control register for endpoint 0 endpt0_rg 1 prevent host retrying NAK ed transactions When a transaction is NAK ed the NAK PID updates the BDT PID field and the token done interrupt is set Required setting when host...

Page 58: ...rface Device HID class devices such as printers and keyboards It is not intended to perform the functions of full Open Host Controller Interface OHCI or Universal Host Controller Interface UHCI compatible host controllers found on PC motherboards Host mode allows bulk isochronous interrupt and control transfers Bulk data transfers are performed at nearly the full USB bus bandwidth Support is provi...

Page 59: ...51 Sample Host Mode Operations Figure 3 Enable Host Mode and Configure a Target Device ...

Page 60: ...52 Figure 4 Full Speed Bulk Data Transfers to a Target Device ...

Page 61: ...ly the USB operates in normal mode with HOST_MODE_EN 0 This mode enables resistor R1 and disables the R2 resistors When the device connects to a PC host the host recognizes that DPLUS is pulled up indicating that a full speed device is attached When the device is in host mode HOST_MODE_EN 1 the R2 resistors are enabled and the R1 resistor is disabled When a USB target connects to the USB the R1 in...

Page 62: ...onnects the USB receive data input to a NRZ serial data stream decoded from the USB D and D signals Typically this signal connects to DATAOUT output from the digital phase lock loop The USB core assumes that this input signal is synchronous to the CLK signal USB End Of Packet EOP The USB end of packet input should be active when a end of packet condition is decoded on the USB D and D signals Typic...

Page 63: ...ns on page 63 CAN Bus Interface on page 84 This chapter assumes you have a working knowledge of the CAN bus protocols Discussions involving CANBUS beyond the scope of DSTni are not covered in this chapter For more information about CANBUS and the higher level protocols that use it as a physical transport medium visit the CAN Automation Web site at http www can cia de Bosch is the originator of the...

Page 64: ...ngle node accepts the message it is also possible to perform broadcast and synchronized communications whereby multiple nodes can accept the same message that is sent in a single transmission Arbitration and Error Checking CAN employs the Carrier Sense Multiple Access with Collision Detection CSMA CD mechanism to arbitrate access to the bus Unlike other bus systems CAN does not use acknowledgement...

Page 65: ... IDE RTR 16 DATA bits Each filter has its own enable flag Transmit Path Three Tx message holding registers with internal priority arbiter Message abort command Receive FIFO Four message deep receive FIFO FIFO status indicator Bus coupler Intel style interface module Full synchronous zero wait states interface Status and configuration interface Programmable Interrupt Controller Listen only mode CAN...

Page 66: ...erroneous operation Each CAN channel has 62 16 bit registers These registers allow for configuration control status and operational data Table 5 3 the 16 bit register mapping for both CAN channels of these registers The hex offsets shown in the table are offset from the base addresses in Table 5 2 Register Summary Table 5 3 CAN Channel Register Summary Hex Offset Register 00 TxMessage_0 ID ID28 13...

Page 67: ..._bitrate_10 0 4E CAN tsegs 50 Acceptance Filter Enable Register AFE_2 0 52 Acceptance Mask Register 0 AMR0 ID28 13 54 ID12 00 IDE RTR 56 D55 48 D63 56 58 Acceptance Code Register 0 ACR0 ID28 13 5A ID12 00 IDE RTR 5C D55 48 D63 56 5E Acceptance Mask Register 1 AMR1 ID28 13 60 ID12 00 IDE RTR 62 D55 48 D63 56 64 Acceptance Code Register 1 ACR1 ID28 13 66 ID12 00 IDE RTR 68 D55 48 D63 56 6A Acceptanc...

Page 68: ...0x12 ID12 ID11 ID10 ID09 ID08 ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00 0x14 D55 D54 D53 D52 D51 D50 D49 D48 D63 D62 D61 D60 D59 D58 D57 D56 0x16 D39 D38 D37 D36 D35 D34 D33 D32 D47 D46 D45 D44 D43 D42 D41 D40 0x18 D23 D22 D21 D20 D19 D18 D17 D16 D31 D30 D29 D28 D27 D26 D25 D24 0x1a D07 D06 D05 D04 D03 D02 D01 D00 D15 D14 D13 D12 D11 D10 D09 D08 0x1c RTR IDE DLC_3 DLC_2 DLC_1 DLC_0 0x1e TX Msg 1 Ctr...

Page 69: ...tx_er_cnt_6 tx_er_cnt_5 tx_er_cnt_4 tx_er_cnt_3 tx_er_cnt_2 tx_er_cnt_1 tx_er_cnt_0 0x42 Error Status Rxgte96 Txgte96 error_stat_1 error_stat_0 0x44 TX RX Msglevel rx_level_1 rx_level_0 tx_level_1 tx_level_0 0x46 IRQ flags rx_msg tx_msg tx_xmit2 tx_xmit1 tx_xmit0 bus_off crc_error form_error ack_error stuff_error bit_error rx_ovr ovr_load arb_loss 0x48 IRQ Enb Reg rx_msg tx_msg tx_xmit2 tx_xmit1 t...

Page 70: ...ID03 ID02 ID01 ID00 IDE RTR 0x68 D55 D54 D53 D52 D51 D50 D49 D48 D63 D62 D61 D60 D59 D58 D57 D56 0x6a Acceptance Mask Register 2 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 0x6c ID12 ID11 ID10 ID09 ID08 ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00 IDE RTR 0x6e D55 D54 D53 D52 D51 D50 D49 D48 D63 D62 D61 D60 D59 D58 D57 D56 0x70 Acceptance Code Register 2 ID28 ID27 ID...

Page 71: ...s contains this message The content of the message buffer must not be changed while the TRX flag is set 3 The TRX flags remain set as long as the message transmit request is pending 4 The successful transfer of a message is indicated by the respective tx_xfer interrupt and by releasing the TRX flag Depending on the tx_level configuration settings an additional interrupt source tx_msg is available ...

Page 72: ... BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 04h FIELD D55 D54 D53 D52 D51 D50 D49 D48 D63 D62 D61 D60 D59 D58 D57 D56 Table 5 8 TxMessage_0 Data 39 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 06h FIELD D39 D38 D37 D36 D35 D34 D33 D32 D47 D46 D45 D44 D43 D42 D41 D40 Table 5 9 TxMessage_0 Data 23 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 08 FIELD D23 D22 D21 D20 D19 D18 D17 D16 D31...

Page 73: ...LC_0 Data Length Code Invalid values are transmitted as they are but only in 8 data bytes TxAbort Transmit Abort Set this flag to request the removal of the pending message in Tx message buffer This occurs the next time when an arbitration loss occurred The flag is cleared when the message either was removed or won arbitration The TRX flag is released at the same time TRX Message Transmit Request ...

Page 74: ... 5 2 RX Message Routing RxMessage 1 MESSAGE FILTERS CAN Module uP Bus CAN BUS RxMessage 0 RxMessage 3 RxMessage 2 To read received messages 1 Wait for rx_msg interrupt 2 MessageReadLoop read message acknowledge message read by writing a 1 to MsgAv register read MsgAv reading a 1 means a new message is available IF MsgAv 1 THEN jump to MessageReadLoop 3 Acknowledge rx_msg interrupt by writing a 1 t...

Page 75: ...ssage ID12 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 32h FIELD ID12 ID11 ID10 ID09 ID08 ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 5 17 Rx Message ID12 Register Definitions Bits Field Name Description 15 3 ID 12 00 Message Identifier for Both Standard and Extended Messages 2 0 Reserv...

Page 76: ... 38h FIELD D23 D22 D21 D20 D19 D18 D17 D16 D31 D30 D29 D28 D27 D26 D25 D24 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 5 23 Rx Message Data 23 Register Definitions Bits Field Name Description 15 0 D 23 24 Message Data Table 5 24 Rx Message Data 7 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 3Ah FIELD D07 D06 D05 D04 D03 D02 D0...

Page 77: ...ansmitted as they are Table 5 28 Rx Message Msg Flags BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 3E FIELD Rx_Fifo2 Rx Fifo1 Rx_Fifo0 Msg Aval RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R R R R W R W R W R W R W Table 5 29 Rx Message Msg Flags Register Definitions Bits Field Name Description 15 8 Reserved 7 5 Rx_Fifo 2 0 Rx FIFO Status These two Read Only flags ...

Page 78: ...dle states 7 0 TE 7 0 Tx_er_cnt Bits The transmitter error counter according to the Bosch CAN specification When it is greater than 255 dec it is fixed at 255 Table 5 32 Error Status Table 5 33 Error Status Register Definitions Bits Field Name Description 15 4 Reserved 3 RX96 Rxgte96 or rx 96 The receiver error counter is greater than or equal to 96 dec 2 TX96 Tx96 or tx 96 The transmitter error c...

Page 79: ...Message Level Register Definitions Bits Field Name Description 15 4 Reserved 3 1 RL 1 0 rx_level 1 0 Sets the rx_msg interrupt threshold 0 at least 1 message in receive FIFO 1 at least 2 messages in receive FIFO 2 at least 3 messages in receive FIFO 3 at least 4 messages in receive FIFO 1 0 TL 1 0 tx_level 1 0 Sets the tx_msg interrupt threshold 0 all tx buffers are empty 1 minimum 2 empty buffers...

Page 80: ... rx_level at least one message is empty 13 TX_XMIT2 Tx Xmit 2 Indicates that the message was successfully sent 12 TX_XMIT1 Tx Xmit 1 Indicates that the message was successfully sent 11 TX_XMIT0 Tx Xmit 0 Indicates that the message was successfully sent 10 BUS_OFF Bus Off State CAN has reached the bus off state 9 CRC_ERR CRC Error CRC error occurred while sending or receiving a message 8 FORM_ERR F...

Page 81: ...flag not set 13 TX_XMIT2 Tx Xmit 2 int1_n group traffic interrupts 1 enable flag set 0 enable flag not set 12 TX_XMIT1 Tx Xmit 1 int1_n group traffic interrupts 1 enable flag set 0 enable flag not set 11 TX_XMIT0 Tx Xmit 0 int1_n group traffic interrupts 1 enable flag set 0 enable flag not set 10 BUS_OFF Bus Off State int2_n group error interrupts 1 enable flag set 0 enable flag not set 9 CRC_ERR ...

Page 82: ... rate detection The two modules can be used in an on chip loop back mode Table 5 40 Interrupt Enable Registers Table 5 41 Interrupt Enable Register Definitions Bits Field Name Description 15 3 Reserved 2 LOOP_BACK Internal Loopback Mode 1 a c Internal loopback 0 a b c d default 1 PASSIVE Active Passive Output is held at R level The CAN module is only listening 1 CAN is passive 0 CAN is active 0 RU...

Page 83: ... configuration parameters Table 5 42 Bit Rate Divisor Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 4Ch FIELD BR10 BR09 BR08 BR07 BR06 BR05 BR04 BR03 BR02 BR01 BR00 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 5 43 Bit Rate Divisor Register Definitions Bits Field Name Description 15 11 Reserved 10 0 BR 10 0 Configuratio...

Page 84: ...g_tseg2 Length 1 of the second time segment Cfg_tseg2 0 is not allowed cfg_tseg2 1 is only allowed in direct sampling mode See Figure 5 4 11 8 TS 1_3 1_0 Cfg_tseg1 Length 1 of the first time segment bit timing It includes the propagation time segment Cfg_tseg1 0 and cfg_tseg1 1 are not allowed See Figure 5 4 7 5 Reserved 4 AUTO_RES Auto Restart 1 after bus off the CAN is restarting automatically a...

Page 85: ...nships Bit Time 1 tseg1 1 tseg2 1 time quanta TQ Sample Point Bittime 1 tseg1 1 tseg2 1 x timequanta timequanta bitrate 1 fclk e g for 1Mbps with fclk 8Mhz set bitrate 0 tseg1 3 and tseg2 2 Observe the following conditions when setting tseg1 and tseg2 tseg1 0 and tseg1 1 are not allowed tseg2 0 is not allowed tseg2 1 is only allowed in direct sampling mode ...

Page 86: ... message filters are disabled no messages are received To receive all messages one message filter must be enabled and programmed with all its fields as don t care The following tables show the Acceptance Mask Register for AMR0 and the Acceptance Code Register ACR0 The registers for AMR1 ACR1 and AMR2 ACR2 are identical except for the offsets See the complete register table at the start of this sec...

Page 87: ...ter ID12 Definitions Bits Field Name Description 15 3 ID 28 13 Message Data 2 IDE Extended Identifier Bit 1 RTR Remote Bit 0 Reserved Table 5 52 Acceptance Mask Register Data 55 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 56h FIELD D55 D54 D53 D52 D51 D50 D49 D48 D63 D62 D61 D60 D59 D58 D57 D56 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R...

Page 88: ...ter ID12 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 5Ah FIELD ID12 ID11 ID10 ID09 ID08 ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00 IDE RTR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 5 57 Acceptance Mask Register ID12 Definitions Bits Field Name Description 15 3 ID 12 0 Message Data 2 IDE Extended Identifier Bit 1 RTR Remote Bit...

Page 89: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 5 61 Arbitration Lost Capture Register Definitions Bits Field Name Description 15 13 Reserved 12 8 FR 4 0 frame_ref_Field This is the frame reference a incoming or outgoing CAN message Values are 00000 stopped 00001 synchronize 00101 interframe 00110 bus_idle 00111 start_of_frame 01000 arbitration...

Page 90: ..._err 011 ack_err 100 stuff_err 101 bit_err 12 8 FR 4 0 frame_ref_Field This is the frame reference a incoming or outgoing CAN message Values are 00000 stopped 00001 synchronize 00101 interframe 00110 bus_idle 00111 start_of_frame 01000 arbitration 01001 control 01010 data 01011 crc 01100 ack 01101 end_of_frame 10000 error_flag 10001 error_echo 10010 error_del 11000 overload_flag 11001 overload_ech...

Page 91: ... Register Definitions Bits Field Name Description 15 STUFFIND Stuff Bit Inserted 1 a stuff bit has been inserted 0 idle 14 RX_BIT Bit State on the Receiver Line 13 TX_BIT Bit State on the Transmitter Line 12 8 FR 4 0 frame_ref_Field This is the frame reference a incoming or outgoing CAN message It is coded as follows 00000 stopped 00001 synchronize 00101 interframe 00110 bus_idle 00111 start_of_fr...

Page 92: ...e Filters RX FIFO TX FIFO INT CTRL STATUS CONFIGURATION START STOP CTRL BUS COUPLER CLK RST PCS1 CAN0 PCS2 CAN1 RD WR ADDR DATA_IN DATA_OUT CAN_RX CAN_TX INT1 CAN0 INT2 CAN1 CAN MODULE CANBUS TRANSCEIVER CANL CANH 82C251 Interface Connections The following sample circuits demonstrate a practical DeviceNet or CANopen interface The wiring diagram for DeviceNet and CANopen connections are shown in Fi...

Page 93: ...AN GND_CAN C18 0 1uf VIN 1 IN 17 U7 DC DC5V VOUT VREC ENA VOUT 8 11 C72 1uf 7 9 ISO_PWR 3 1 2 C17 10uf 1 2 5V L1 NFM61R30T472T1 SYNC 18 C112 10uf 1 2 R108 1 K ERR 12 C13 10uf 1 2 V V Z1 D1 P4KE33CA SB160 R11 3 9K R10 R9 1 5K PZT2907AT1 Q1 24V 1 3 2 4 I C2 0 1uf U14 IN OUT GND GND LM2940IMP 5 0 1 3 2 4 C1 0 1uf C3 22uf 5_BUS 1 3 2 1 3 P_C05V P_C0G P_C05V and P_C0G Pos 1 2 for Isolated Power P_C05V ...

Page 94: ... VCC GND 8 5 C67 0 01uf R191 680 7 3 3v 2 R193 270 CAN_TX 3 4 5_CAN 470 6 RXD 4 TXD U18 PCA82C251 CANL CANH 6 CAN 7 CAN C10 0 01uf GND_CAN 3 V 8 2 GND_CAN GND RS 1 GND_CAN C9 0 01uf 1 VCC GND 8 5 C12 0 01uf R190 680 7 5v F 2 R189 CAN_RX 3 4 6 U19 HCPL 0601 C68 0 01uf GND_CAN ...

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