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LANGER
EMV-Technik
DE-01728 Bannewitz
[email protected]
www.langer-emv.de
E1
The different tools included with the E1 allow four measurement strategies to clarify even the most
complex of EMC immunity faults.
5.1 - Analysis of the interference current paths; injection directly into the printed circuit board with the
SGZ 21 generator
5.2 - Localisation of weak points in the layout and components using field sources
5.3 - Monitoring of critical logic signals of the printed circuit board
5.4 - Measurement of the burst-related magnetic fields to trace the disturbance current
The faults are narrowed down in systematic steps. The first step is always the
analysis of the interference
current paths
and a reproduction of the fault patterns from the standard compliance test. Different
measurement strategies (5.2 to 5.4) can be applied depending on the behaviour of the device under test
and the developer's own theory about this behaviour.
5.1
Analysis of the interference current paths
The disturbance current i is injected via the mains connecting cable, for example, in the standard
compliance test. The disturbance current spreads across the modules and structural parts in the device.
Electric and magnetic disturbance fields are produced. These fields may encounter weak points at any place
and trigger malfunctions. But the exact location of the weak point cannot be identified (Figure 17).
The E1 can be used to inject disturbance current into individual paths at random (Figure 19). The
malfunction is triggered if an electric or magnetic field, which is generated by this, encounters the weak
point. Hence, the fault location is narrowed down. Fault localisation begins as soon as a malfunction is
triggered in the device under test. Individual sections of the device under test such as individual modules,
individual cable connections, small areas of a large module, etc. are initially investigated.
5.1.1
Basic principle of magnetic coupling – two-pole injection into the device under test
The objective of the first step is to reproduce the fault patterns from the standard compliance test. The first
test is thus performed with the device completely set up. The device under test is contacted with the
SGZ 21 in accessible places and a disturbance current is injected. This is demonstrated by way of an
example in Figure 19. One pole of the SGZ 21 is connected to the terminal of the auxiliary power supply.
The other pole is connected to the housing (PE). The interference current path closes to the housing via
supply conductor runs, discharge capacitors and discharge paths. The magnetic fields of the burst current
penetrate the upper printed circuit board and interfere with the processor system. A clever choice of
injection paths marked red in Figure 19 allows the developer to draw conclusions about the approximate
location of the actual interference and its mechanism of action.
If the disturbance current flows through the device under test via conductors or large capacitances (in the
nF range), it encounters a constantly low-resistance path in the area of the device under test. This requires
disturbance currents with a high intensity and corresponding strong magnetic fields. Only small electric
fields have to be expected in this case.
The occurrence of the sought-after malfunction in this situation suggests magnetic interference.
In the case of devices under test with several printed circuit boards or with large modules it is helpful to
guide the disturbance current through only individual printed circuit boards or sections of the module and
thus narrow down the sensitive area.
