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4.3.1.1 Status Byte Register
The status byte register, typically referred to as the status byte, is a non-latching,
read-only register that contains all of the summary bits from the register sets. The
status of the summary bits are controlled from the register sets as explained in
section 4.3.2.1 to section 4.3.2.5. The status byte also contains the Master Summary
Status (MSS) bit. This bit is used to report if any of the summary bits are set via the
*STB? command. The status of the MSS bit is controlled by the summary bits and the
service request enable register.
4.3.1.2 Service Request Enable Register
The service request enable register determines which summary bits in the status byte
will set the MSS bit of the status byte. The user may write to or read from the service
request enable register. Each status byte summary bit is logically ANDed to the corre-
sponding enable bit of the service request enable register. When a service request
enable register bit is set by the user, and the corresponding summary bit is set in the
status byte, the MSS bit of the status byte will be set.
4.3.1.3 Conditional Registers
Each register set (except the standard event register set) includes a condition register
as shown in FIGURE 4-1. The condition register constantly monitors the instrument
status. The data bits are real-time and are not latched or buffered. The register is
read-only.
4.3.1.4 Event Registers
Each register set includes an event register as shown in FIGURE 4-1. Bits in the event
register correspond to various system events and latch when the event occurs. Once
an event bit is set, subsequent events corresponding to that bit are ignored. Set bits
remain latched until the register is cleared by a query command (such as *ESR?) or a
*CLS command. The register is read-only.
4.3.1.5 Enable Registers
Each register set includes an enable register as shown in FIGURE 4-1. An enable regis-
ter determines which bits in the corresponding event register will set the summary
bit for the register set in the status byte. The user may write to or read from an enable
register. Each event register bit is logically ANDed to the corresponding enable bit of
the enable register. When an enable register bit is set by the user, and the correspond-
ing bit is set in the event register, the output (summary) of the register will be set,
which in turn sets the master summary status bit of the status byte register.
4.3.1.6 Register Read/Write Behavior
4.3.1.6.1 Reading Registers
Any register in the status system may be read using the appropriate query command.
Some registers clear when read, others do not (section 4.3.1.6.3). The response to a
query will be a decimal value that corresponds to the binary-weighted sum of all bits
in the register (TABLE 4-1). The actual query commands are described later through-
out section 4.5.
TABLE 4-1
Binary weighting of an 8-bit register
Position
B7
B6
B5
B4
B3
B2
B1
B0
Decimal
128
64
32
16
8
4
2
1
Weighting
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
Example: If bits 0, 2, and 4 are set, a query of the register will return a decimal value of 21 (1+4+16)
Summary of Contents for Measure Ready M91 FastHall
Page 6: ...MeasureReady M91 FastHall Measurement Controller ...
Page 10: ...MeasureReady M91 FastHall Measurement Controller ...
Page 64: ...54 cHAPTER 3 Operation MeasureReady M91 FastHall Measurement Controller ...
Page 156: ...146 cHAPTER 4 Computer Interface Operation MeasureReady M91 FastHall Measurement Controller ...
Page 160: ...150 cHAPTER 5 Options and Accessories MeasureReady M91 FastHall Measurement Controller ...
Page 174: ...164 cHAPTER 6 Service MeasureReady M91 FastHall Measurement Controller ...
