SSD50NBT
Hardware Integration Guide
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/bluetooth
4
© Copyright 2015 Laird. All Rights Reserved
Americas: +1-800-492-2320
Europe: +44-1628-858-940
Hong Kong: +852 2923 0610
Scope
This document describes key hardware aspects of the Laird SSD50NBT system in
package (SIP) modules providing either SDIO or USB bus interface for WLAN
connection and UART/PCM for Bluetooth connection. This document is intended
to assist device manufacturers and related parties with the integration of this
radio into their host devices. Data in this document is drawn from a number of
sources and includes information found in the Qualcomm Atheros (QCA)
QCA6004 and Cambridge Silicon Radio Ltd. (CSR) CSR8811 A08 data sheets issued
in July 2011, along with other documents provided from QCA and CSR.
The Laird 50-series SIP is currently in development stage and this document is
preliminary. The information in this document is subject to change.
Please contact Laird to obtain the most
recent version of this document.
SSD50NBT
F
EATURES
S
UMMARY
The Laird SSD50NBT device features are described in
Table 1
.
Table 1: SSD50NBT features
Feature
Description
Radio Front End
Integrates the complete transmit/receive RF paths including baluns, coexistence band pass filter,
diplexer, switches, power amplifier, low noise amplifier, and reference crystal oscillator.
Enhanced WLAN/BT
Coexistence
Algorithms
Enhanced important use cases including:
PCM/I2S digital audio interface
BT stereo audio (A2DP)
BT data transfer profiles (such as OPP and FTP)
BT2.1+EDR
BT-LE
Flexible radio architecture ensures simple customization for future use cases.
Power Management
Uses power-saving techniques including:
Gating clocks to idle or inactive blocks
Fast start and settling circuits to reduce Tx power
Active duty cycles
CPU frequency scaling
Pre-Calibration
RF system tested and calibrated in production.
Internal Sleep Clock
Integrated on-chip low power sleep clock to regulate internal timing.
Multiple Interface
Support
SDIO 2.0 (50 MHz, 4-bit and 1-bit) or USB for WLAN
HS-UART for Bluetooth HCI (compatible with any upper layer Bluetooth stack)
Advanced 802.11n
Half Guard Interval and Frame Aggregation for high throughput
Space Time Block Coding (STBC) Rx for improved downlink robustness over range
Low Density Parity Check (LDPC) for improved uplink and downlink robustness over range
Reference
Frequency
Incorporates a 26 MHz reference frequency source in package
Sleep regulated and gated to enable the internal crystal to be powered down when the device is in
sleep mode
BT shares the clock from the Wi-Fi chip.
Wi-Fi cannot be turned off or in reset when running BT.