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DVK-SU60-2230C Development Kit 

User Guide 

Embedded Wireless Solutions Support Center: 
http://ews-support.lairdtech.com 
www.lairdtech.com/wireless

 

13 

© Copyright 2017 Laird. All Rights Reserved 

Americas: +1-800-492-2320 

Europe: +44-1628-858-940 

Hong Kong: +852 2923 0610

 

 

PCIE_W_DISABLE_N (SW5) 

PCIe host indication to disable the WLAN function of the device (Input) (Active Low) 

 

Figure 5: DVK-SU60-2230C 1.8V power supply 

0 

–

 Disable the WLAN 

1 

–

 Normal mode 

▪

 

PCIE_W_DISABLE_N can accept an input of 3.3 volts. 

▪

 

PCIE_W_DISABLE_N may be driven by the host 

▪

 

PCIE_W_DISABLE_N must be high for normal operation 

An internal pull-up resister on this pin. 

3.3.2

 

PDn (SW6) 

Full Power-Down (Input) (Active Low) 

0 

–

 Full power-down mode 

1 

–

 Normal mode 

▪

 

PDn can accept an input of 1.8 volts 

▪

 

PDn may be driven by the host 

Summary of Contents for DVK-SU60-2230C

Page 1: ...A User Guide M 2 Development Kit DVK SU60 2230C Version 1 0 ...

Page 2: ...upport Center http ews support lairdtech com www lairdtech com wireless 2 Copyright 2017 Laird All Rights Reserved Americas 1 800 492 2320 Europe 44 1628 858 940 Hong Kong 852 2923 0610 REVISION HISTORY Version Date Notes Approver 1 0 29 July 2017 Initial Release Jay White ...

Page 3: ... 4 1 3 Key Features 5 1 4 Understanding the Development Board 6 3 Functional Blocks 7 1 5 Pin Definitions 7 1 5 1 M 2 Key E Socket 7 1 5 2 SDIO Pin Header 9 1 5 3 PCIe Golden Finger 10 1 6 Power Supply 11 1 7 Tact Switch 12 1 7 1 PCIE_W_DISABLE_N SW5 13 1 7 2 PDn SW6 13 1 7 3 PMU_EN SW7 14 1 8 4 wire UART Serial Interface 14 1 8 1 UART Mapping 14 1 8 2 UART Interface Driven by USB 14 1 8 3 UART In...

Page 4: ...the following Development board The development board has the required SU60 2230C module installed onto it and exposes all the various hardware interfaces available Power options USB cable Type A to micro B The cable also provides serial communications via the FTDI USB RS232 converter chip on the development board DC barrel plug with clips for connection to external power supply IDC cable x Suppli...

Page 5: ...0 or 60 series module installed on board Power supply options for powering development board from USB External DC supply SDIO interface Regulated 3 3 V for powering the 50 or 60 series modules Optional regulated 1 8 V for powering the VCCIO for FTDI chip USB to UART bridge FTDI chip USB interface for Wifi or BT M 2 UART can be interfaced to USB PC using the USB UART bridge External UART source usi...

Page 6: ... 2017 Laird All Rights Reserved Americas 1 800 492 2320 Europe 44 1628 858 940 Hong Kong 852 2923 0610 2 2 Understanding the Development Board Figure 1 Development board FTDI FT232R CON5 DC Jack SW1 Slide SW USB2 USB to UART mPCIe CON2 SDIO USB3 USB 2 0 M 2 Module 32 KHz OSC J23 J21 J23 SW7 SW6 SW5 LED1 LED3 LED2 J22 J15 J17 J16 J1 J5 J8 J3 J6 J4 J7 J18 ...

Page 7: ...e Input if Slave mode N C 9 SDIO CLK I PU 1 8V SDIO 4 bit Mode Clock Input N C 10 PCM_SYNC I O 1 8V PCM Sync Pulse Signal Output if Master mode Input if Slave mode N C 11 SDIO CMD I O 1 8V SDIO 4 bit Mode Command Response N C 12 PCM_IN I 1 8V PCM Data N C 13 SDIO DATA0 I O PU 1 8V SDIO 4 bit Mode DATA line Bit 0 N C 14 PCM_OUT O 1 8V PCM Data N C 15 SDIO DATA1 I O PU 1 8V SDIO 4 bit Mode DATA line...

Page 8: ...n external sleep clock of 32 768KHz with minimum 250ppm is required for power saving mode 51 GND Ground GND 52 PERST0 I PD 3 3V PCIe host indication to reset the device input active low N C 53 CLKREQ0 I O 3 3V PCIe clock request input output active low GND 54 W_DISABLE2 I 3 3V Enable input for all Regulators inside the sU60 SIPT Note DO NOT float this pin Pull up to 3 3V with 100K for normal opera...

Page 9: ...supply 75 GND Ground GND 76 GND Ground GND 77 GND Ground GND 3 1 2 SDIO Pin Header Figure 2 DVK SU60 2230C SDIO Pin Header Table 2 SDIO pin header Pin Name Type Voltage Ref Description If Not Used 1 GND Ground GND 2 SDIO DATA2 I O PU 1 8V SDIO 4 bit Mode DATA line Bit 2 N C 3 GND Ground GND 4 SDIO DATA3 I O PU 1 8V SDIO 4 bit Mode DATA line Bit 3 N C 5 GND Ground GND 6 SDIO CMD I O 1 8V SDIO 4 bit...

Page 10: ...I O 3 3V PCIe wake signal input output active low N C 2 PCIE_3V3 Power 3 3V module power supply 3 4 GND Ground GND 5 6 7 CLKREQ0 I O 3 3V PCIe clock request input output active low GND 8 9 GND Ground GND 10 11 REFCLKn0 I 1 8V PCIe Differential Clock input Negative N C 12 13 REFCLKp0 I 1 8V PCIe Differential Clock input Positive N C 14 15 GND Ground GND 16 17 18 GND Ground GND 19 20 W_DISABLE1 I PU...

Page 11: ... LED2 O PU 3 3V LED indicator for BT with 10mA drive capability N C 47 48 49 50 GND Ground GND 51 52 PCIE_3V3 Power 3 3V module power supply 3 2 Power Supply DC Jack CON5 USB Connector USB2 USB3 SW2 12V 5V 5V DC DC 12V 5V 5V 5V DC DC 5V 3 3V 3 3V Pin Header J5 3 3V Pin Header J3 Pin Header J4 50 60 series M 2 Module 3 3V 3 3V 5V PCIe Interface SDIO Interface Figure 3 DVK SU60 2230C power supply Th...

Page 12: ...ct regulated 5 volts The development board has a 1 8 volt regulator for the VCCIO of FTDI Chip Figure 4 DVK SU60 2230C power supply for VCCIO of FTDI chip On the development board the power domain M2_3V3 supplies the M 2 module only The header connectors J3 J4 J5 can be used to measure the current of power domain M2_3V3 REG_1V8 supplies the FTDI chip IO only 3 3 Tact Switch 3 3 1 The development b...

Page 13: ...host indication to disable the WLAN function of the device Input Active Low Figure 5 DVK SU60 2230C 1 8V power supply 0 Disable the WLAN 1 Normal mode PCIE_W_DISABLE_N can accept an input of 3 3 volts PCIE_W_DISABLE_N may be driven by the host PCIE_W_DISABLE_N must be high for normal operation An internal pull up resister on this pin 3 3 2 PDn SW6 Full Power Down Input Active Low 0 Full power down...

Page 14: ...USB UART convertor chip or through a breakout header connector J15 J16 J17 and J18 Refer to Figure 6 Note M 2 module provides 4 wire UART interface on the HW VIH is from 1 26V to 2 2V VIL is from 0 4V to 0 54V 3 4 1 UART Mapping UART connection on the 50 and 60 series modules and FTDI IC are shown in table below Refer to Figure 6 to see how the 50 and 60 series module UART is mapped to the breakou...

Page 15: ...Source UART interface driven by external UART source The M 2 module UART interface TX RX CTS RTS is presented at a 2 54 mm 0 1 in pitch headers J15 J16 J17 and J18 To allow the M 2 UART interface to be driven from the breakout header connector J15 J16 J17 and J18 Development board must be powered from DC jack CON5 and switch SW1 is in position DC JACK 5V 50 60 series M 2 Module FT232R J15 BT_UART_...

Page 16: ...tions of J20 for PCM signal are shown in below table Table 5 PCM pins J20 Description Pin 1 GND Pin 2 PCM_IN Pin 3 PCM_OUT Pin 4 PCM_BCLK Pin 5 PCM_SYNC Pin 6 GNDGND Note VIH is from 1 26V to 2 2V VIL is from 0 4V to 0 54V 3 7 LTE Coexistence The development kit provides the LTE coexistence signal on J21 The pin descriptions of J21 for LTE coexistence signal are shown in below table Table 6 LTE co...

Page 17: ...power LED3 WLAN status Active Low 4 ADDITIONAL DOCUMENTATION Laird offers a variety of documentation and ancillary information to support our customers through the initial evaluation process and ultimately into mass production Additional documentation includes DVK SU60 2230C User Manual DVK SU60 2230C Schematics 50 and 60 series M 2 Module User Manual Hardware Datasheet and Integration Guide For a...

Page 18: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Laird DVK SU60 2230C DVK ST60 2230C ...

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