BT830 Hardware Integration Guide
Version 1.3
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/bluetooth
20
Laird Technologies
Americas: +1-800-492-2320
Europe: +44-1628-858-940
Hong Kong: +852-2923-0610
Figure 12: PCM Slave Timing Short Frame Sync
PCM_CLK and PCM_SYNC Generation
BT830 has two methods of generating PCM_CLK and PCM_SYNC in master mode:
Generating these signals by DDS from BT830internal 4MHz clock. Using this mode limits PCM_CLK to 128, 256
or 512 kHz and PCM_SYNC to 8 kHz.
Generating these signals by DDS from an internal 48MHz clock enables a greater range of frequencies to be
generated with low jitter but consumes more power. To select this second method, set bit to
48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the length
of PCM_SYNC is either 8 or 16 cycles of PCM_CLK, determined by LONG_LENGTH_SYNC_EN in
PSKEY_PCM_CONFIG32.
describes PCM_CLK frequency when generated from the internal 48MHz clock:
Equation 0.1: PCM_CLK Frequency Generated Using the Internal 48MHz Clock
Set the frequency of PCM_SYNC relative to PCM_CLK using
Equation 0.2: PCM_SYNC Frequency Relative to PCM_CLK
CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an example, to
generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set SKEY_PCM_LOW_JITTER_CONFIG to 0x08080177.
