E20-10
User Manual
Table 5-5. Acquisition stopping conditions
Acquisition stopping conditions
Implemented in
version E20-10
Notes
Software asynchronous stopping
A, B
based on frame edges
On number
M
of recorded frames
acquisition restartable (
see notes 1, 2
) under
settled start conditions, for example, to
implement start-stop acquisition mode
B
0
≤
M
≤ 16777215,
where,
M
-integral
Note1:
In FPGA firmware of version 2.00.03 (details on firmware versions see in p.
for restarting under any start condition it is required to activate software restart on
upper software level (i.e. single start on condition is executed in practice). In FPGA
2.00.05 firmware the additional program start is not required under additional startup
condition
"on transmission through given signal level in selected channel" and stopping
condition "on number of M recorded frames", due completing of the next stopping condition
fulfillment the additional data acquisition start will begin automatically upon completing of
new start condition fulfillment (i.e. multiple start on condition in practice). For another
start conditions
FPGA 2.00.05 firmware is similar to 2.00.03 firmware.
Note 2:
In future FPGA firmwares it is technically possible to implement software control of
single-multiple start modes (in the context of note 1) on any specific start condition
upon stopping "
on number
M
of recorded frames". Make an enquiry to
L-Card
, if such
mode is required to solve Your problems.
Visual illustration of
E20-10
synchronization modes is given in diagrams
Frame
size equal to 4, interframe delay duration equal to 6 ADC conversion frequency periods are taken as
an example on diagrams; frame is configurated on sequence sampling of all 4 channels. Under such
configurations the data numeration frequency per ADC channel will make
10
1
given ADC
conversion frequency.
Common case
for applying all possible synchronization conditions (except "on
level" synchronization conditions which are discussed individually) is shown on top diagram. In
E20-10
of revision A the software data acquisition start (or on START signal edge) was applied,
and upon start data were certainly recorded in FIFO buffer until data acquisition software stopping
from upper level was sent (despite of frame edges). In
E20-10
of revision В you may use the
configurations on additional recording conditions on signal edge, for example, as shown in diagram,
in ADC 3-rd channel. In this case, frames will not fall in FIFO buffer (and, thus, will not fall in
USB) till given additional condition will be fulfilled. As soon as the condition is fulfilled in the
current frame, the data begining from the next frame will be fed into the FIFO and can be rolled
back via USB. Blockage of transmission of given amount of frames starting from acquisition can be
settled in revision B individually or as the second additional condition.
Stopping based on given amount of frames collection is provided in revision B except for
asynchronous software acquisition stopping; furthermore, stopping edge will comply with end of
last collected frame. In practice, this capability allows to carry out acquisition start-stop operation
under preselected start mode (pay attention on notes to
capabilities).
and as shown in diagrams, START signal behavior does not
depend on additional start conditions if it is configurated "on output ("slave").
Data acquisition on signal level synchronization mode (above or below given threshold) in
selected (on diagram - on 3-rd) physical ADC channel is shown on bottom diagram
) (in