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VITA 57 Development Kit User's Guide

Development

SD.DT.F79-0e

Page

3

The following shows the FPGA sources files:

Now, you could add your Verilog files and libraries, modify the current files to match your application. You will
find hereafter the snapshot of the VM6250 VITA 57 project as example.

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Summary of Contents for VITA 57

Page 1: ...VITA 57 Development Kit User s Guide SD DT F79 0e May 2011 If it s embedded it s Kontron ...

Page 2: ...011 Kontron AG All rights reserved All data is for information purposes only and not guaranteed for legal purposes Information has been carefully checked and is believed to be accurate however no responsibility is assumed for inaccuracies Kontron and the Kontron logo and all other trademarks or registered trademarks are the property of their respective owners and are recognized Specifications are ...

Page 3: ...y include names company logos and trademarks which are registered trademarks and therefore proprietary to their respective owners Environmental Protection Statement This product has been manufactured to satisfy environmental protection requirements where possible Many of the components used structural parts printed circuit boards connectors batteries etc are capable of being recycled Final disposi...

Page 4: ...the MSB Signal names ending with an asterisk or a hash denote active low signals all other signals are active high Signal names follow the PICMG 2 0 R3 0 CompactPCI Specification and the PCI Local Bus 2 3 Specification For Your Safety Your new Kontron product was developed and tested carefully to provide all features necessary to ensure its compliance with electrical safety requirements It was als...

Page 5: ... They can cause short circuits and damage the batteries or conductive circuits on the board General Instructions on Usage In order to maintain Kontron s product warranty this product must not be altered or modified in any way Changes or modifications to the device which are not explicitly approved by Kontron and described in this manual or received from Kontron s Technical Support as a special han...

Page 6: ... Linux Prompt Binary file 7 3 2 Upload User Flash with JTAG Probe mcs file 7 3 3 Upload Flash on FMC 7 Chapter 4 Troubleshooting 8 4 1 Configuration Check 8 4 2 FPGA Check 8 4 3 FMC EEPROM Check 9 4 4 FMC IOs Check 9 4 4 1 FMC GPIOn signals 9 4 4 2 FMC TXn RXn signals 11 4 4 2 1 Enable buffers 12 4 4 2 2 Test a channel 12 4 5 Low Level Debug with IO Command 14 Chapter 5 Additional Information 16 5...

Page 7: ...d as examples are available for Linux distributions and are coded in C and python language Modifying some FPGA code IP s like I2C SPI is highly inadvisable All modification will be done at customer s own risks I2C and SPI IPs were dedicated to Kontron boards so any changes could break some functionalities 1 2 Use cases This documents meet the following cases New FPGA application development New FP...

Page 8: ...pters will describe an example of a FPGA application development and how to use the tools to generate an FPGA image 2 1 FPGA Kontron Source Code The VITA 57 project example file tree is the following The entry point of the Kontron source code is the file Topserial v describing a VITA 57 implementation example ...

Page 9: ...ent SD DT F79 0e Page 3 The following shows the FPGA sources files Now you could add your Verilog files and libraries modify the current files to match your application You will find hereafter the snapshot of the VM6250 VITA 57 project as example ...

Page 10: ...it User s Guide Development Page 4 SD DT F79 0e 2 2 FPGA Code Compilation The following is an example of compilation based on VM6250 VITA 57 case You will find hereafter the snapshot of the VM6250 VITA 57 project as example ...

Page 11: ...Select your application dedicated file into the hierarchy window here Topserial v then right click on Generate program file into the process window and click on Run or ReRun to generate the bit or bin or both files file You can select to generate several kind of files using the processes properties into the process menu ...

Page 12: ...VITA 57 Development Kit User s Guide Development Page 6 SD DT F79 0e The generation process is launched if no errors appear bit file will be generated into Worklib directory ...

Page 13: ...formation The flash upload is also platform dependant so refer also to Your VITA 57 BSP documentation for more informations about it 3 2 Upload User Flash with JTAG Probe mcs file At first a mcs image must be generated so use the Impact tool from the ISE Design Suite to create a mcs file from the bit file obtained by the image generation This could be done only for rescue images in case of trouble...

Page 14: ...the user and password from the VITA 57 BSP documentation of the board and log in 4 1 Configuration Check This is a basic verification of the installed software rpm qa grep VITA57 VITA57_BSP 1 0 2 6 25_10356 vm6250 fc9 ppc smp 11004 ppc rpm qa grep kernel kernel smp devel 2 6 25 10356 vm6250 fc9 ppc kernel smp 2 6 25 10356 vm6250 fc9 ppc kernel bootwrapper 2 6 25 09135 vm6250 fc9 ppc kernel devel 2...

Page 15: ... IOs available on this front panel FMC GPIOn and FMC TXn RXn signals 4 4 1 FMC GPIOn signals Set odd FMC GPIOs GPIO1 3 5 7 9 as outputs others as inputs gpio c 9 s GPIO_Control v 0x155 Set output GPIOs to 1 gpio c 9 s GPIO_DataOut v 0x155 Check the GPIO levels all must be at level 1 because they are outputs at level 1 or because thay are inputs connected to the outputs gpio c 9 g GPIO_In GPIO_In 0...

Page 16: ... gpio c 9 g GPIO_In GPIO_In 0x00000000 To see the current value of all registers of a channel binary and hex format use the u option For example gpio c 9 u Channel 9 10 GPIOs GPIO_Control XXXXXXXXXXXXXXXXXXXXXX1010101010 0x000002AA GPIO_DataOut XXXXXXXXXXXXXXXXXXXXXX0000000000 0x00000000 GPIO_In XXXXXXXXXXXXXXXXXXXXXX0000000000 0x00000000 GPIO_IntMask XXXXXXXXXXXXXXXXXXXXXX1111111111 0x000003FF GP...

Page 17: ...ggle XXXXXXXXXXXXXXXXXXXXXX0000000000 0x00000000 GPIO_IntStatus XXXXXXXXXXXXXXXXXXXXXX0000000000 0x00000000 GPIO_GlobalStatus 00000000000000000000000000000000 for more info on GPIO command gpio h 4 4 2 FMC TXn RXn signals These signals can be set for RS232 or RS422 485 mode On FMC SER0 PCB B the TXn buffers are enabled by the DXEN for TX1 to TX14 and DXEN1516 for TX15 and TX16 signals when set to ...

Page 18: ...command above is suitable for FMC SER0 PCB B On FMC SER0 PCB A the RS232 or RS422 485 mode is controlled by DXEN1516 for all TXn RXn to set to RS232 gpio c 8 s GPIO_DataOut v 0x1 to set to RS422 485 gpio c 8 s GPIO_DataOut v 0x3 4 4 2 2 Test a channel The test below is done on channel 0 TX1 RX1 TX2 RX2 It must also be done on other channels 1 to 7 by replacing the c 0 with c 1 to c 7 Set TX signal...

Page 19: ...st read TX1 RX1 RX2 0 TX2 1 GPIO_In 0x00000002 gpio c 0 s GPIO_DataOut v 0x0 TX1 0 TX2 0 gpio c 0 g GPIO_In must read TX1 RX1 TX2 RX2 0 GPIO_In 0x00000000 Check TX RX signals when configured for RS232 The level set on TX1 must be also read on RX1 and the level set on TX2 must be also read on RX2 TX1 TX2 and RX1 RX2 are independant gpio c 0 s GPIO_DataOut v 0x8 TX1 1 TX2 0 gpio c 0 g GPIO_In must r...

Page 20: ... connector on the FMC SER0 front panel Set VADJ to 3V3 in REGI0 general purpose register at offset 0x380 if not yet done root localhost io 4 w 0x80000b80 0x08000000 root localhost io 4 r l 0x4 0x80000b80 80000b80 08000000 Set signals controlling buffer output enable as outputs by setting channel 8 GPIO control register at offset 0x200 root localhost io 4 w 0x80000a00 0x03000000 root localhost io 4...

Page 21: ...0 but also RX1 1 and RX2 0 because of loopback root localhost io 4 w 0x80000804 0x08000000 root localhost io 4 r l 0x4 0x80000808 80000808 09000000 Set TX1 0 and TX2 1 should reread TX1 0 and TX2 1 but also RX1 0 and RX2 1 because of loopback root localhost io 4 w 0x80000804 0x02000000 root localhost io 4 r l 0x4 0x80000808 80000808 06000000 root localhost Set TX1 and TX2 to 0 should reread TX1 TX...

Page 22: ...ected 5 TX3 Connected to RX3 6 RX4 Connected to TX4 7 GND3 Not connected 8 TX5 Connected to RX5 9 RX6 Connected to TX6 10 GND4 Not connected 11 TX7 Connected to RX7 12 RX8 Connected to TX8 13 GND5 Not connected 14 TX9 Connected to RX9 15 RX10 Connected to TX10 16 GND6 Not connected 17 TX11 Connected to RX11 18 RX12 Connected to TX12 19 GND7 Not connected 20 TX13 Connected to RX13 21 RX14 Connected...

Page 23: ...IO6 1Kohms to GPIO5 35 RX11 Already connected 36 TX10 Already connected 37 GPIO5 Already connected 38 RX9 Already connected 39 TX8 Already connected 40 GPIO4 1Kohms to GPIO3 41 RX7 Already connected 42 TX6 Already connected 43 GPIO3 Already connected 44 RX5 Already connected 45 TX4 Already connected 46 GPIO2 1Kohms to GPIO1 47 RX3 Already connected 48 TX2 Already connected 49 GPIO1 Already connect...

Page 24: ...1 103 LA6N RX8 HA23N K23 230 23 C12 23 to pin 24 K15 H14 138 LA7N TX7 HB5P E24 235 22 A11 22 J15 H13 128 LA7P TX8 HB5N E25 245 24 A12 24 L14 G12 117 LA8P RX9 HB1P J24 239 25 C13 25 to pin 26 K14 G13 127 LA8N RX10 HB1N J25 249 27 C14 27 to pin 28 L17 D15 144 LA9N TX9 HB9P E27 265 26 A13 26 L18 D14 134 LA9P TX10 HB9N E28 275 28 A14 28 N16 C14 133 LA10P RX11 HB11P J30 299 33 C17 33 to pin 34 M16 C15 ...

Page 25: ...o pin 55 A14 D24 234 LA23N GPIO14 HB14N K35 350 55 C28 55 D13 H28 278 LA24P GPIO15 HB12P F31 306 54 A27 54 1k to pin 56 D14 H29 288 LA24N GPIO16 HB12N F32 316 56 A28 56 E14 G27 267 LA25P GPIO17 HB17P K37 370 57 C29 57 1k to pin 59 F14 G28 277 LA25N GPIO18 HB17N K38 380 59 C30 59 E15 D26 254 LA26P GPIO19 HB20P F37 366 58 A29 58 1k to pin 60 D15 D27 264 LA26N GPIO20 HB20N F38 376 60 A30 60 E17 C26 2...

Page 26: ...0 VITA57 schematics FPGA pin GND HA18N J19 189 7 C4 7 GND HA22P J21 209 17 C9 17 GND HA22N J22 219 19 C10 19 GND HB7P J27 269 29 C15 29 GND HB7N J28 279 31 C16 1 31 GND HB0P K25 250 41 C21 41 GND HB0N K26 260 43 C22 43 1 P2 pin A16 may be REAR2_RTS or HB13N depending on VX6060 equipment P2 pin C16 may be REAR1_RTS or HA7N depending on VX6060 equipment 2 With FMC SER0 PCB A DXEN enables TXn outputs...

Page 27: ...uffers 232 or 422 485 is set by the MODE signal DXEN1516 With FMC SER0 PCB B these signals control the LEDs and also override the default mode of TXn RXn buffers set by the switches level 1 RS422 or 485 level 0 RS232 LED1R_SW1 TX1 RX1 TX2 RX2 TX3 RX3 TX4 RX4 LED1G_SW2 TX5 RX5 TX6 RX6 TX7 RX7 TX8 RX8 LED2R_SW3 TX9 RX9 TX10 RX10 TX11 RX11 TX12 RX12 LED2G_SW4 TX13 RX13 TX14 RX14 TX15 RX15 TX16 RX16 4...

Page 28: ...33 0 4 98 16 34 00 150 rue Marcelin Berthelot BP 244 sales kontron com ZI TOULON EST support kom sa kontron com 83078 TOULON CEDEX France For further information about other Kontron products please visit our Internet web site www kontron com If it s embedded it s Kontron ...

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