ECX-BYT - User Guide, Rev. 1.0
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// 43
Pin
Signal
Note
5
LVDS_A2-
6
7
GND
8
LVDS_ACLK-
9
LV
10
LVDS_A3-/NC
11
/NC
12
LVDS_B0-
13
14
GND
15
LVDS_B1-
16
17
GND
18
LVDS_B2-
19
20
LVDS_BCLK-
21
LV
22
LVDS_B3-/NC
23
/NC
24
GND
25
DDC_DATA
26
VDDEN
27
DDC_CLK
28
+3.3V / +5V *
29
+3.3V / +5V*
30
+3.3V / +5V*
* Panel Power can be selected by JP5.
Table 38: Signal Description
Signal
Description
LVDS_A0..A3
LVDS A Channel data
LVDS_ACLK
LVDS A Channel clock
LVDS_B0..B3
LVDS B Channel data
LVDS_BCLK
LVDS B Channel clock
VDDEN
Output Display Enable
DDC_DATA
DDC channel Data
DDC_CLK
DDC Channel Clock
