AM4011
Configuration
ID 1022-1626, Rev. 1.0
Page 4 - 11
P R E L I M I N A R Y
4.4.6
Reset Status Register
The Reset Status Register is used to determine the reset source.
Table 4-13: Reset Status Register
REGISTER NAME
RESET STATUS REGISTER
ADDRESS
0x285
BIT
NAME
DESCRIPTION
RESET
VALUE
ACCESS
7
PHRST
Power-on host reset detection
0 = System reset generated by software (warm reset)
1 = System reset generated by power-on (cold reset)
Writing a ’1’ to this bit clears this bit.
N/A
R/W
6-4
Res.
Reserved
N/A
R
3
MRST
MMC reset the host processor
0 = System reset generated by power-on reset
1 = System reset generated by MMC
Writing a ’1’ to this bit clears the bit.
0
R/W
2-1
Res.
Reserved
00
R
0
WRST
Watchdog timer reset the host processor
0 = System reset generated by power-on reset
1 = System reset generated by Watchdog timer
Writing a ’1’ to this bit clears the bit.
0
R/W
