Kontron 104-AD128, User Manual

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5-4
104-ADIO128 (AD128) User’s Guide
the next conversion. There is a 50mS start-up delay before a conversion from the full power-
down state.
The ADC has a Sample and Hold circuit controlled by the Acquisition Mode bit. A control byte with
this bit set low will select an acquisition interval of 3uS after which a conversion will begin. A
noisy signal may require more integration. A control byte with this bit set high will start a user-
determined acquisition period, conversion will begin when a 2
nd
control byte is sent with bit 5
set low. Bits 0, 1, and 2 must be the same value but the power state may be changed.
Bit 4, the range bit, doubles the input voltage range when set.
Bit 3 selects bipolar mode when set.
The channel selection bits direct one of the eight analog inputs connected to the ADC’s
multiplexor to the Sample and Hold circuit. Bits 2, 1, and 0 make a binary value equal to the
channel number.
Bit 7 Bit 6 Device Mode
0 0 Normal Operation, selects the external (to the ADC) clock
mode, a 2MHz clock frequency is applied
0 1 Internal clock mode, not appropriate for this circuit,
unexpected events may occur if this mode is selected
1 0 Standby power-down, supply current will typically be 700uA
1 1 Full power-down, supply current will be 120uA worst case
Range (Bit 4) Bipolar / Unipolar (Bit 3) Input Range
0 0 0 - 5V
1 0 0 - 10V
0 1 ±
5V
1 1 ±
10V