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2 Programming the Test Set
STATus Subsystem
Questionable Frequency Register
"Questionable Frequency Condition " on page 75
"Questionable Frequency Enable " on page 75
"Questionable Frequency Event Query " on page 76
"Questionable Frequency Negative Transition " on page 76
"Questionable Frequency Positive Transition " on page 76
Questionable Frequency Condition
This query returns the decimal value of the sum of the bits in the Questionable Frequency Condition
register.
The data in this register is continuously updated and reflects the current conditions.
Mode
All
Remote Command
:STATus:QUEStionable:FREQuency:CONDition?
Example
STAT:QUES:FREQ:COND?
Preset
0
Status Bits/OPC
dependencies
Sequential command
Initial S/W Revision
Prior to A.02.00
Questionable Frequency Enable
This command determines which bits in the Questionable Frequency Condition Register will set bits in the
Questionable Frequency Event register, which also sets the Frequency Summary bit (bit 5) in the
Questionable Register. The variable <integer> is the sum of the decimal values of the bits you want to
enable.
Mode
All
Remote Command
:STATus:QUEStionable:FREQuency:ENABle <integer>
:STATus:QUEStionable:FREQuency:ENABle?
Example
STAT:QUES:FREQ:ENAB 2 Frequency Reference Unlocked will be reported to the Frequency
Summary of the Status Questionable register.
Preset
32767
Min
0
Max
32767
Status Bits/OPC
dependencies
Sequential command
Initial S/W Revision
Prior to A.02.00
Sequence Analyzer User's & Programmer's Reference
75