Checking the
Keysigh
t N4877A
7
Connect the N4877A to the N4903B
Disable the outputs of the
J-BERT and use a 2.4 mm
cable (m-m) and connect
the pattern generator's
Data Out port to the
Input port of the N4877A.
1
Mount the SMA 50 Ohm
termination on the unused
Data Out port of the pattern
generator using the SMA
to 2.4 mm adapter.
2
Using a 3.5 mm SMA cable (m-m)
and connect the Recovered Clock Out
port of the N4877A with CLK IN port
of the N4903B Error Detector.
3
4
Using a 3.5 mm/2.4 mm
adapter to connect the
Demux Data Out1 port
to the Error Detector's
Data Input port.
Configure The N4877A to
Input Source: Electrical Data Differential
Nominal Data Rate: 8 Gb/s
Loop Bandwidth: Rate Dependant
Data Rate Divider: 1667
Enable Auto Re-Lock: Checked
Clock Out Divide Ratio: Auto unchecked,
Select 1÷ 2
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6
7
Restore the N4903B
user interface from
the windows taskbar.
5
Launch the N4877A Remote
GUI from the Windows Start
Menu.
8
Set the N4903B PG to:
Bit rate: 8 Gb/s
Jitter Generation: Off
Data Out Levels:
- 0.5 V Amplitude
0 V Offset
Pattern: PRBS 2^15-1
Enable the outputs of
the J-BERT.
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-
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9
Set the N4903B ED to:
Pattern: PRBS 2^15-1
Input Configuration: Single Ended Normal
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10
Minimize the N4903B
user interface and
maximize the N4877A
Remote GUI.
11
Check whether the N4877A
is locked, if the CDR is not
locked, then click the
Re-Lock button.
Verify whether the N4877A is working properly.
The indications are:
N4877A reports locked.
N4903B displays the expected frequency at the Error Detector
(Calculated from settings at the N4877A:
Nominal Data Rate/Output Divider)
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–
14
BER should be 0.0 after
Auto Alignment on the
PRBS bitstream.
13
Perform Auto-Alignment
on the Error Detector.
12
After the N4877A entered locked
state, maximize the N4903B user
interface. The Error Detector should
no longer report clock loss.
For more details, refer to the Help and the
User Guide of N4877A and N4903B.
