Keysight Technologies D9020DDRC, Manual

Page: 52 / 370

3 Measurement Clock Tests
36 DDR2(+LP) Compliance Testing Methods of Implementation
Cycle to Cycle Period Jitter - tJIT(cc) - Test Method of Implementation
This test is applicable to the Rising Edge Measurement as well as Falling Edge Measurement. The
purpose of this test is to measure the difference in the clock period between two consecutive clock
cycles. The tJIT(cc) Rising Edge Measurement measures the clock period from the rising edge of a
clock cycle to the next rising edge. The tJIT(cc) Falling Edge Measurement measures the clock period
from the falling edge to falling edge. The test will show a fail status if the total failed waveforms is
greater than 0.
Signals of Interest
Mode Supported: DDR2, LPDDR2
Signal cycle of interest: READ or WRITE
Signal(s) of Interest:
• Clock Signal
Signals required to perform the test on the oscilloscope:
• Pin Under Test, PUT - any signal of interest, as defined above
Test Definition Notes from the Specification
Table 5 Specific Note 35
Parameter Symbol DDR2-667 DDR2-800 Units Notes
Min Max Min Max
Cycle to Cycle Period Jitter tJIT(cc) -250 250 -200 200 ps 35
Table 6 Specific Note 30
Parameter Symbol DDR2-1066 Units Notes
Min Max
Cycle to Cycle Period Jitter tJIT(cc) -180 180 ps 30
Table 7 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Max.
Frequency
*4
533 466 400 333 266 233 200 166 133 100 MHz
Clock Timing
Maximum
Clock Jitter
between two
consecutive
clock cycles
(with
allowed jitter) t
JIT
(cc),
allowed
Max 180 190 200 220 240 260 280 300 360 500 ps