Keysight Technologies D9020DDRC, Manual

Page: 317 / 370

DDR2(+LP) Compliance Testing Methods of Implementation 301
Command and Address Timing (CAT) Tests 17
Test References
See Table 41 - Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) and Table 42 -
Timing Parameters by Speed Grade (DDR2-667 and DDR2-800) in the
JEDEC Standard JESD79-2E .
See Table 41 - Timing Parameters by Speed Grade (DDR2-1066) in the JESD208 .
Also see Table 104 - CA and CS_n Setup and Hold Base-Values for 1V/ns in the JESD209-2B .
PASS Condition
The measured time interval between the address/control setup time and the respective clock
crossing point should be within the specification limit.
Measurement Algorithm
1 Pre-condition the oscilloscope settings.
2 Trigger on both edges (rising or falling) of the address/control signal under test.
3 Find all of the crossings on the rising edge of the signal under test that cross V
IH(AC)
.
4 Find all of the crossing on the falling edge of the signal under test that cross V
IL(AC)
.
5 For all crossings, locate the nearest Clock crossing that crosses 0V.
6 Take the time difference between the signal under test’s crossing and the corresponding clock
crossing as tIS.
7 Collect all measured tIS.
8 Report the worst tIS measured as the test result.
9 Compare the test result against the compliance test limit.