Keysight Technologies D9020DDRC, Manual

Page: 263 / 370

DDR2(+LP) Compliance Testing Methods of Implementation 247
Data Strobe Timing (DST) Tests 15
Measurement Algorithm
1 Acquire and split read and write burst of the acquired signal.
2 Take the first valid READ burst found.
3 Find the Data tLZBeginPoint of this burst.
4 Find RL Clock edge (tDQSCK clock edge reference).
• Find all DQS rising middle crossing points in the burst.
• Find the first DQS rising edge by searching for the earliest rising crossing point in all of the
found DQS middle crossing points.
• Find the closest Clock-DQS (the Clock middle crossing point that is closest to the first DQS
rising edge).
• Find the RL Clock edge (tDQSCK clock edge reference) which is the Clock middle crossing
point immediately before the closest Clock-DQS to tDQSCK Delay (cycle). By default, tDQSCK
Delay is one cycle. For example, if tDQSCK Delay = 1 then the tDQSCK Clock point is the Clock
middle crossing point that is prior to the closest Clock-DQS. If tDQSCK Delay = 3 then the
tDQSCK Clock point is the Clock middle crossing point three clock cycles before the closest
Clock-DQS. tDQSCK Delay is configurable in the configuration page.
5 Compare the Data tLZ begin point to the RL Clock edge as the test result.
Mathematically, the test result = Data tLZ begin point - RL Clock edge point.
6 Display the test result by going to the measurement location on the waveform and locate the
marker to Data tLZ begin point and Clock middle cross point of the test result.
7 Compare the test result against the compliance test limit.