Keysight Technologies D9020DDRC, Manual

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DDR2(+LP) Compliance Testing Methods of Implementation 149
Differential Signals AC Input Parameters Tests 10
Test References
See Table 22 - Differential Input AC Logic Level in the JEDEC Standard JESD79-2E and Table 22 -
Differential Input AC Logic Level in the JESD208 .
PASS Condition
The calculated magnitude of the differential voltage of the test signals pair should be within the
conformance limits of the V
ID(AC)
value.
Measurement Algorithm
1 Sample/acquire data waveforms.
2 Use Subtract FUNC to generate the differential waveform from the two source inputs.
3 Find the first 10 differential CLK crossing that cross 0V.
4 Within first and second CLK crossing region, perform V
TOP
on CLK,GND OR /CLK,GND
depending on which one is the positive pulse in the current region. Next, perform V
BASE
on
CLK,GND OR /CLK,GND depending on which one is the negative pulse in the current region.
Calculate V
ID(AC)
= V
TOP
- V
BASE
.
5 Perform the previous step on all pairs of CLK crossing until 10 measurement results are collected.
6 Determine the worst result from the set of V
ID(AC)
measured.