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DDR2(+LP) Compliance Testing Methods of Implementation

91

Single-Ended Signals AC Input Parameters Tests

4

Measurement Algorithm

1 Acquire and split read and write bursts of the acquired signal.
2 Take the first valid READ burst found.
3 Find all valid signal rising edges in this burst. A valid signal rising edge starts at the V

OL(AC)

crossing and ends at the following V

OH(AC)

crossing.

4 For all valid signal rising edges, find the transition time, T

R

, which is the time that starts at the

V

OL(AC)

crossing and ends at the following V

OH(AC)

crossing. Then calculate

SRQseR = [V

OH(AC)

- V

OL(AC)

]/T

R

.

5 Determine the worst result from the set of SRQseR measured.

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Summary of Contents for D9020DDRC

Page 1: ...Keysight D9020DDRC DDR2 LP Compliance Test Application Methods of Implementation ...

Page 2: ... software described in this document are furnished under a license and may be used or copied only in accor dance with the terms of such license Restricted Rights Legend If software is for use in the performance of a U S Government prime contract or subcon tract Software is delivered and licensed as Commercial computer software as defined in DFAR 252 227 7014 June 1995 or as a commercial item as de...

Page 3: ...le Ended signal TEST Cycle Based on Test Definition Required Connection Type to Perform Test on Scope Opt Read Write DQ DQS CK ADD Ctrl Data Mask Ctrl DQ DQS CK ADD Ctrl Data Mask Ctrl CS tJIT per tJIT cc tERR nper tCH avg tCL avg tJIT duty tCK avg VIH ac VIH dc VIL ac VIL dc SlewR SlewF AC Overshoot AC Undershoot VID ac VIX ac VOX ac tAC tDQSCK tHZ DQ tLZ DQS tLZ DQ ...

Page 4: ...te DQ DQS CK ADD Ctrl Data Mask Ctrl DQ DQS CK ADD Ctrl Data Mask Ctrl CS tDQSQ tQH tDQSS tDQSH tDQSL tDSS tDSH tWPST tWPRE tRPRE tRPST tDS base tDH base tDS1 base tDH1 base tIS base tIH base Eye Diagram Read Eye Diagram Write Table 1 DDR2 Cycles and Signals NOTE 1 Single Ended signal 2 Differential signal 3 2 x Single Ended signal ...

Page 5: ...d its configuration Shows you how to make oscilloscope connections to the device under test Automatically checks for proper oscilloscope configuration Automatically sets up the oscilloscope for each test Allows you to determine the number of trials for each test with the new multi trial run capability Allows you to customize the test limits in the application which determines the pass or and fail ...

Page 6: ...R Oscilloscopes D9020DDRC DDR2 LP Compliance Test Application version 1 27 or higher RAM reliability test software 1169A 1168A 1134A 1132A or 1131A InfiniiMax probe amplifiers N5381A or E2677A differential solder in probe head N5382A or E2675A differential browser probe head N5425A ZIF probe head with N5426A or N5451A ZIF tip accessories E2678A differential socketed probe head Any computer motherb...

Page 7: ...ndershoot tests probing and method of implementation Chapter 10 Differential Signals AC Input Parameters Tests describes the VID AC differential input voltage tests and VIX AC differential cross point voltage tests The VIHdiff and VILdiff tests for both AC and DC are also described Chapter 11 Differential Signal AC Output Parameters Tests contains information on the VOX AC differential cross point...

Page 8: ...e Table File Threshold Settings DDR Debug Tool Selecting Tests Configuring Tests Critical Configuration Verifying Physical Connections Running tests Options to Start Test Runs Settings to Optimize Test Runs Configuring Automation in the Test Application Using Script for Automation Using Files for Automation Running Automation Script or Files Viewing Results Viewing HTML Test Report Exiting the Tes...

Page 9: ...is available at www keysight com find contactus Phone or Fax United States tel 800 829 4444 fax 800 829 4433 Canada tel 877 894 4414 fax 800 746 4866 China tel 800 810 0189 fax 800 820 2816 Europe tel 31 20 547 2111 Japan tel 81 426 56 7832 fax 81 426 56 7840 Korea tel 080 769 0800 fax 080 769 0900 Latin America tel 305 269 7500 Taiwan tel 0800 047 866 fax 0800 286 331 Other Asia Pacific Countries...

Page 10: ...10 DDR2 LP Compliance Testing Methods of Implementation ...

Page 11: ...ing the License Key 37 Using Keysight License Manager 5 37 Using Keysight License Manager 6 38 40 2 Preparing to Take Measurements Calibrating the Oscilloscope 26 Starting the DDR2 LP Compliance Test Application 27 Online Help Topics 29 3 Measurement Clock Tests Probing for Measurement Clock Tests 32 Test Procedure 32 Clock Period Jitter tJIT per Test Method of Implementation 34 Signals of Interes...

Page 12: ...plementation 41 Signals of Interest 41 Test Definition Notes from the Specification 41 Test References 41 Pass Condition 41 Measurement Algorithm 41 Average HIGH Pulse Width tCH avg Test Method of Implementation 43 Signals of Interest 43 Test Definition Notes from the Specification 43 Test References 43 Pass Condition 43 Measurement Algorithm 44 Absolute HIGH Pulse Width tCH abs Test Method of Imp...

Page 13: ...K avg Test Method of Implementation 51 Signals of Interest 51 Test Definition Notes from the Specification 51 Test References 51 51 Pass Condition 52 Measurement Algorithm 52 Absolute Clock Period tCK abs Test Method of Implementation 53 Signals of Interest 53 Test Definition Notes from the Specification 53 Test References 53 Pass Condition 53 Measurement Algorithm 53 4 Single Ended Signals AC Inp...

Page 14: ...ignals of Interest 64 Test Definition Notes from the Specification 64 Test References 64 PASS Condition 65 Measurement Algorithm 65 VIH DC Test for DQS Test Method of Implementation 66 Signals of Interest 66 Test Definition Notes from the Specification 66 Test References 66 PASS Condition 67 Measurement Algorithm 67 VIH DC Test for Address Control Test Method of Implementation 68 Signals of Intere...

Page 15: ... 76 Signals of Interest 76 Test Definition Notes from the Specification 76 Test References 76 PASS Condition 77 Measurement Algorithm 77 VIL DC Test for DQS Test Method of Implementation 78 Signals of Interest 78 Test Definition Notes from the Specification 78 Test References 78 PASS Condition 79 Measurement Algorithm 79 VIL DC Test for Address Control Test Method of Implementation 80 Signals of I...

Page 16: ...st Method of Implementation 88 Signals of Interest 88 Test Definition Notes from the Specification 88 Test References 89 PASS Condition 89 Measurement Algorithm 89 SRQseR 40ohm Test Method of Implementation 90 Signals of Interest 90 Test Definition Notes from the Specification 90 Test References 90 PASS Condition 90 Measurement Algorithm 91 SRQseF 40ohm Test Method of Implementation 92 Signals of ...

Page 17: ... Test References 96 PASS Condition 96 Measurement Algorithm 96 VOL AC Test Method of Implementation 97 Signals of Interest 97 Test Definition Notes from the Specification 97 Test References 97 PASS Condition 97 Measurement Algorithm 97 VOL DC Test Method of Implementation 98 Signals of Interest 98 Test Definition Notes from the Specification 98 Test References 98 PASS Condition 98 Measurement Algo...

Page 18: ... 106 Test References 106 PASS Condition 106 Measurement Algorithm 106 6 Single Ended Signals VIH VIL Data Mask Tests Probing for Single Ended Signals VIH VIL Data Mask Tests 108 Test Procedure 108 VIHDQ AC Test Method of Implementation 110 Signals of Interest 110 Test Definition Notes from the Specification 110 Test References 110 PASS Condition 110 Measurement Algorithm 111 VIHDQ DC Test Method o...

Page 19: ...2 PASS Condition 122 Measurement Algorithm 123 VSEL AC strobe Test Method of Implementation 124 Signals of Interest 124 Test Definition Notes from the Specification 124 Test References 124 PASS Condition 124 Measurement Algorithm 124 8 Single Ended Signals AC Parameters Tests for Clock Probing for Single Ended Signals AC parameter tests for Clock 126 Test Procedure 126 VSEH AC clock Test Method of...

Page 20: ...ershoot Tests 134 Test Procedure 134 AC Overshoot Test Method of Implementation 136 Signals of Interest 136 Test Definition Notes from the Specification 136 137 Test References 138 PASS Condition 138 Measurement Algorithm 138 AC Undershoot Test Method of Implementation 139 Signals of Interest 139 Test Definition Notes from the Specification 139 140 Test References 141 PASS Condition 141 Measuremen...

Page 21: ...est for Clock Test Method of Implementation 152 Signals of Interest 152 Test Definition Notes from the Specification 152 Test References 153 PASS Condition 153 Measurement Algorithm 153 VIHdiff AC Test for DQS Test Method of Implementation 154 Signals of Interest 154 Test Definition Notes from the Specification 154 Test References 154 PASS Condition 154 Measurement Algorithm 155 VIHdiff AC Test fo...

Page 22: ...ences 164 PASS Condition 164 Measurement Algorithm 165 VILdiff DC Test for DQS Test Method of Implementation 166 Signals of Interest 166 Test Definition Notes from the Specification 166 Test References 166 PASS Condition 166 Measurement Algorithm 167 VILdiff DC Test for Clock Test Method of Implementation 168 Signals of Interest 168 Test Definition Notes from the Specification 168 Test References ...

Page 23: ... Test References 179 PASS Condition 179 Measurement Algorithm 179 SRQdiffF 60ohm Test Method of Implementation 180 Signals of Interest 180 Test Definition Notes from the Specification 180 Test References 180 PASS Condition 180 Measurement Algorithm 180 VOHdiff AC Test Method of Implementation 181 Signals of Interest 181 Test Definition Notes from the Specification 181 Test References 181 PASS Cond...

Page 24: ...0 PASS Condition 190 Measurement Algorithm 190 14 Clock Timing CT Tests Probing for Clock Timing Tests 192 Test Procedure 192 tAC DQ Output Access Time from CK CK Test Method of Implementation 194 Signals of Interest 194 Test Definition Notes from the Specification 194 Test References 194 PASS Condition 195 Measurement Algorithm 195 tDQSCK DQS Output Access Time from CK CK Test Method of Implement...

Page 25: ... Delta Short Test Test Method of Implementation 204 Signals of Interest 204 Test Definition Notes from the Specification 204 Test References 204 PASS Condition 204 Measurement Algorithm 205 tDQSCKDM Test DQSCK Delta Medium Test Test Method of Implementation 206 Signals of Interest 206 Test Definition Notes from the Specification 206 Test References 206 PASS Condition 206 Measurement Algorithm 207 ...

Page 26: ...als of Interest 218 Test Definition Notes from the Specification 218 218 Test References 219 PASS Condition 219 Measurement Algorithm 219 tQH DQ DQS Output Hold Time From DQS Test Method of Implementation 220 Signals of Interest 220 Test Definition Notes from the Specification 220 Test References 221 PASS Condition 221 Measurement Algorithm 221 tDQSS DQS Latching Transition to Associated Clock Edg...

Page 27: ...lementation 230 Signals of Interest 230 Test Definition Notes from the Specification 230 Test References 231 PASS Condition 231 Measurement Algorithm 231 tWPST Write Postamble Test Method of Implementation 232 Signals of Interest 232 Test Definition Notes from the Specification 232 232 Test References 233 PASS Condition 233 Measurement Algorithm 233 tWPRE Write Preamble Test Method of Implementati...

Page 28: ...nals of Interest 242 Test Definition Notes from the Specification 242 Test References 242 PASS Condition 242 Measurement Algorithm 243 tLZ DQS Test Low Power DQS Low Impedance Time From Clock Test Method of Implementation 244 Signals of Interest 244 Test Definition Notes from the Specification 244 Test References 244 PASS Condition 244 Measurement Algorithm 245 tLZ DQ Test Low Power DQ Low Impedan...

Page 29: ...Time above VIHdiff AC below VILdiff AC Test Method of Implementation 252 Signals of Interest 252 Test Definition Notes from the Specification 252 Test References 252 PASS Condition 252 Measurement Algorithm 253 16 Data Timing Tests Probing for Data Timing Tests 256 Test Procedure 257 tDS base Differential DQ and DM Input Setup Time Test Method of Implementation 259 Signals of Interest 259 Test Def...

Page 30: ...ls of Interest 279 Test Definition Notes from the Specification 279 Test References 279 PASS Condition 279 Measurement Algorithm 280 tDH1 base Single Ended DQ and DM Input Hold Time Test Method of Implementation 281 Signals of Interest 281 Test Definition Notes from the Specification 281 Test References 281 PASS Condition 281 Measurement Algorithm 282 tDS1 derate Single Ended DQ and DM Input Setup...

Page 31: ...d of Implementation 292 Signals of Interest 292 Test Definition Notes from the Specification 292 Test References 292 PASS Condition 292 Measurement Algorithm 292 tDS DQ and DM Input Setup Time Differential VREF based Test Method of Implementation 293 Signals of Interest 293 Test Definition Notes from the Specification 293 Test References 293 PASS Condition 293 Measurement Algorithm 294 tDH DQ and ...

Page 32: ... Signals of Interest 304 Test Definition Notes from the Specification 304 Test References 309 PASS Condition 310 Measurement Algorithm 310 tIH derate Address and Control Input Hold Time with Derating Support Test Method of Implementation 311 Signals of Interest 311 Test Definition Notes from the Specification 311 Test References 316 PASS Condition 317 Measurement Algorithm 317 tVAC CS CA Time Abov...

Page 33: ...es 324 PASS Condition 324 Measurement Algorithm 324 tIHCKEb CKE Input Hold Time Boot Parameter Test Method of Implementation 325 Signals of Interest 325 Test Definition Notes from the Specification 325 Test References 325 PASS Condition 325 Measurement Algorithm 325 18 Custom Mode Read Write Eye Diagram Tests Probing for Custom Mode Read Write Eye Diagram Tests 328 Test Procedure 328 User Defined ...

Page 34: ... Methods of Implementation Contents Probe Calibration 339 Connecting the Probe for Calibration 339 Verifying the Connection 341 Running the Probe Calibration and Deskew 343 Verifying the Probe Calibration 347 20 InfiniiMax Probing ...

Page 35: ...esting Methods of Implementation 1 Installing the DDR2 LP Compliance Test Application Installing the Software 36 Installing the License Key 37 If you purchased the D9020DDRC DDR2 LP Compliance Test Application separately you need to install the software and license key ...

Page 36: ...software see D9020DDRC release notes To ensure that you have the minimum version select Help About Infiniium from the main menu 2 To obtain the DDR2 LP Compliance Test Application go to Keysight website http www keysight com find D9020DDRC 3 The link for DDR2 LP Compliance Test Application will appear Double click on it and follow the instructions to download and install the application software ...

Page 37: ...res 2 Copy the Host ID that appears on the top pane of the application Note that x indicates numeric values Figure 1 Viewing the Host ID information in Keysight License Manager 5 To install one of the procured licenses using Keysight License Manager 5 application 1 Save the license files on the machine where you wish to run the Test Application and its features 2 Launch Keysight License Manager 3 ...

Page 38: ...License Manager 6 1 Launch Keysight License Manager 6 on your machine where you wish to run the Test Application and its features 2 Copy the Host ID which is the first set of alphanumeric value as highlighted in Figure 3 that appears in the Environment tab of the application Note that x indicates numeric values Figure 3 Viewing the Host ID information in Keysight License Manager 6 ...

Page 39: ... on the machine where you wish to run the Test Application and its features 2 Launch Keysight License Manager 6 3 From the Home tab use one of the options to install each license file Figure 4 Home menu options to install licenses on Keysight License Manager 6 For more information regarding installation of procured licenses on Keysight License Manager 6 refer to Keysight License Manager 6 Supporti...

Page 40: ...1 Installing the DDR2 Compliance Test Application 40 DDR2 LP Compliance Testing Methods of Implementation ...

Page 41: ...cilloscope 26 Starting the DDR2 LP Compliance Test Application 27 Before running the DDR2 automated tests you should calibrate the oscilloscope and probe No test fixture is required for this DDR2 application After the oscilloscope and probe have been calibrated you are ready to start the DDR2 LP Compliance Test Application and perform the measurements ...

Page 42: ...more than 5 degrees Celsius from the calibration temperature internal calibration should be performed again The delta between the calibration temperature and the present operating temperature is shown in the Utilities Calibration menu NOTE If you switch cables between channels or other oscilloscopes it is necessary to perform cable and probe calibration again Keysight recommends that once calibrat...

Page 43: ...g in the computer system where the Device Under Test DUT is attached This software performs tests to all unused RAM in the system by producing a repetitive burst of read write data signals to the DDR2 memory 2 To start the DDR2 LP Compliance Test Application From the Infiniium oscilloscope s main menu choose Analyze Automated Test Apps DDR2 Test Figure 5 The DDR2 LP Compliance Test Application ...

Page 44: ...s show which tests have passed failed or not been run and there are indicators for the test groups Configure Lets you configure test parameters like memory depth This information appears in the HTML report Connect Shows you how to connect the oscilloscope to the device under test for the tests to be run Run Tests Starts the automated tests If the connections to the device under test need to be cha...

Page 45: ...tting Up the Test Environment Set Mask File Derate Table file Threshold Settings DDR Debug Tool Selecting Tests Configuring Tests Critical Configuration Verifying Physical Connections Running Tests Options to Start Test Runs Settings to Optimize Test Runs Configuring Automation in the Test Application Using Script for Automation Using Files for Automation Running Automation Script or Files Viewing...

Page 46: ...2 Preparing to Take Measurements 30 DDR2 LP Compliance Testing Methods of Implementation ...

Page 47: ...bsolute HIGH Pulse Width tCH abs Test Method of Implementation 45 Average Low Pulse Width tCL avg Test Method of Implementation 46 Absolute Low Pulse Width tCL abs Test Method of Implementation 48Absolute Clock Period tCK abs Test Method of Implementation 53 Half Period Jitter tJIT duty Test Method of Implementation 49 Average Clock Period tCK avg Test Method of Implementation 51 This section prov...

Page 48: ...ocedure 1 Start the automated test application as described in Preparing to Take Measurements on page 25 2 Ensure that the RAM reliability test software is running on the computer system where the DDR2 Device Under Test DUT is attached This software will perform a test on all the unused RAM on the system by producing a repetitive burst of read write data signals to the DDR2 memory 3 Connect the di...

Page 49: ...elect Tests tab and check the tests you want to run Check the parent node or group to check all the available tests within the group 9 Follow the DDR2 Test application s task flow to set up the configuration options run the test and view the test results Figure 7 Selecting Measurement Clock Tests ...

Page 50: ...cope Pin Under Test PUT any signal of interest as defined above Test Definition Notes from the Specification Test References See Specific Note 35 in the JEDEC Standard JESD79 2E and Specific Note 30 in the JESD208 and Table 103 in the JESD209 2B Table 2 Specific Note 35 Parameter Symbol DDR2 667 DDR2 800 Units Notes Min Max Min Max Clock Period Jitter tJIT per 125 125 100 100 ps 35 Table 3 Specifi...

Page 51: ...een period 2 with the average and save the answer as a measurement result 5 Continue with the same procedures until you complete the comparison for period 200 with the average By now 200 measurement results are generated 6 Slide the window by one and measure the average of 2 201 7 Compare period 2 with the new average Continue the comparison for period 3 4 200 201 By now 200 more measurement resul...

Page 52: ...erest Mode Supported DDR2 LPDDR2 Signal cycle of interest READ or WRITE Signal s of Interest Clock Signal Signals required to perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined above Test Definition Notes from the Specification Table 5 Specific Note 35 Parameter Symbol DDR2 667 DDR2 800 Units Notes Min Max Min Max Cycle to Cycle Period Jitter tJIT cc 250 250 ...

Page 53: ...JIT cc measurement value should be within the conformance limits as specified in the JEDEC specification Measurement Algorithm Example input test signal Frequency 1 KHz Number of cycles acquired 202 1 Measure the difference between every adjacent pair of periods 2 Generate 201 measurement results 3 Check the results for the smallest and largest values worst case values 4 Compare the test results a...

Page 54: ...e Specification Table 8 Specific Note 35 Parameter Symbol DDR2 667 DDR2 800 Units Notes min max min max Cumulative error across 2 cycles tERR 2per 175 175 150 150 ps 35 Cumulative error across 3 cycles tERR 3per 225 225 175 175 ps 35 Cumulative error across 4 cycles tERR 4per 250 250 200 200 ps 35 Cumulative error across 5 cycles tERR 5per 250 250 200 200 ps 35 Cumulative error across n cycles n 6...

Page 55: ...350 486 Cumulative error across 5 cycles tJIT 5 per allowed Min 188 199 209 230 251 272 293 314 377 524 ps Max 188 199 209 230 251 272 293 314 377 524 Cumulative error across 6 cycles tJIT 6 per allowed Min 200 211 222 244 266 288 311 333 399 555 ps Max 200 211 222 244 266 288 311 333 399 555 Cumulative error across 7 cycles tJIT 7 per allowed Min 209 221 232 256 279 302 325 248 418 581 ps Max 209...

Page 56: ...esults are generated 7 Slide the big window by one and start comparing the average of periods 2 and 3 with the new big window average until the comparison for periods 200 and 201 with the big window is completed By now 199 more measurements are added with the total of 398 measurement values 8 Slide the big window by one again and repeat the same procedures By now 199 more measurements are added wi...

Page 57: ...he Specification Test References See Table 103 in the JEDEC Standard JESD209 2B Pass Condition The tERR measurement value from 13 cycle through 50 cycle should be within the conformance limits as specified in the JEDEC specification Measurement Algorithm Example input test signal Frequency 1 KHz Number of cycles acquired 202 tERR 13 50per executes tERR 13per through tERR 50per For tERR 13per 1 Cal...

Page 58: ...he average of periods 2 14 and end by comparing the average of periods 189 201 6 Slide the window by one again and repeat the same procedures 7 Calculate the compliance upper and lower limits for tERR 13per Upper limit 1 0 68ln n tJIT per max where n 13 Lower limit 1 0 68ln n tJIT per min where n 13 NOTE tJIT per max and tJIT per min vary depending on the speed grade selected 8 Check all tERR 13pe...

Page 59: ...rd JESD79 2E Table 41 Timing Parameters by Speed Grade DDR2 1066 in the JESD208 and Table 103 in the JESD209 2B Pass Condition The tCH measurement value should be within the conformance limits as specified in the JEDEC specification Table 12 Timing Parameters by Speed Grade DDR2 667 and DDR2 800 Parameter Symbol DDR2 667 DDR2 800 Units Specific Notes Min Max Min Max Average clock HIGH pulse width ...

Page 60: ...urement result is generated 3 Measure the width of the high pulses 2 201 and determine the average value for this window By now one measurement result is generated with the total of two measurement results 4 Measure the width of the high pulses 3 202 and determine the average value for this window By now one measurement result is generated with the total of three measurement results 5 Check the to...

Page 61: ...CH measurement value should be within the conformance limits as specified in the JEDEC specification Measurement Algorithm Example input test signal Frequency 1 KHz Number of cycles acquired 202 1 Find the average period tCK avg for cycle 1 202 2 Find the maximum high pulse width PWMAX s for cycle 1 202 3 Find the minimum high pulse width PWMIN s for cycle 1 202 4 Calculate PWMAX tCK PWMAX s tCK a...

Page 62: ...DEC Standard JESD79 2E Table 41 Timing Parameters by Speed Grade DDR2 1066 in the JESD208 and Table 103 in the JESD209 2B Pass Condition The tCL measurement value should be within the conformance limits as specified in the JEDEC specification Table 16 Timing Parameters by Speed Grade DDR2 667 and DDR2 800 Parameter Symbol DDR2 667 DDR2 800 Units Notes Min Max Min Max Average clock LOW pulse width ...

Page 63: ...rement result is generated 3 Measure the width of the low pulses 2 201 and determine the average value for this window By now one measurement result is generated with the total of two measurement results 4 Measure the width of the low pulses 3 202 and determine the average value for this window By now one measurement result is generated with the total of three measurement results 5 Check the total...

Page 64: ...tCL measurement value should be within the conformance limits as specified in the JEDEC specification Measurement Algorithm Example input test signal Frequency 1 KHz Number of cycles acquired 202 1 Find the average period tCK avg for cycle 1 202 2 Find the maximum low pulse width PWMAX s for cycle 1 202 3 Find the minimum low pulse width PWMIN s for cycle 1 202 4 Calculate PWMAX tCK PWMAX s tCK av...

Page 65: ... Clock Signal Signals required to perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined above Test Definition Notes from the Specification Test References See Specific Note 35 in the JEDEC Standard JESD79 2E Specific Note 30 in the JESD208 and Table 103 in the JESD209 2B Table 20 Specific Note 35 Parameter Symbol DDR2 667 DDR2 800 Units Notes Min Max Min Max Dut...

Page 66: ...ult 5 Continue the same procedures until the comparison for high pulse width 200 with the average is completed By now 200 measurement results are generated 6 Slide the window by one and measure the average of 2 201 7 Compare high pulse width 2 with the new average Continue the comparison for high pulse width 3 4 200 201 By now 200 more measurement results are added with the total of 400 values 8 S...

Page 67: ... any signal of interest as defined above Test Definition Notes from the Specification Test References See Table 42 Timing Parameters by Speed Grade DDR2 667 and DDR2 800 in the JEDEC Standard JESD79 2E Table 41 Timing Parameters by Speed Grade DDR2 1066 in the JESD208 and Table 103 in the JESD209 2B Table 23 Timing Parameters by Speed Grade DDR2 667 and DDR2 800 Parameter Symbol DDR2 667 DDR2 800 ...

Page 68: ...g window of 200 cycles 2 Calculate the average period value for periods 1 200 By now one measurement result is generated 3 Calculate the average period value for periods 2 201 By now one measurement result is generated with the total of two measurement results 4 Calculate the average period value for periods 3 202 By now one measurement result is generated with the total of three measurement resul...

Page 69: ...perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined above Test Definition Notes from the Specification Test References See Table 103 in the JESD209 2B Pass Condition The tCK abs measurement value should be within the conformance limits as specified in the JEDEC specification Measurement Algorithm Example input test signal Frequency 1 KHz Number of cycles acqui...

Page 70: ...3 Measurement Clock Tests 54 DDR2 LP Compliance Testing Methods of Implementation ...

Page 71: ...for DQS Test Method of Implementation 78 VIL DC Test for Address Control Test Method of Implementation 80 SlewR Test for DQ DM DQS Test Method of Implementation 82 SlewR Test for Address Control Clock Test Method of Implementation 84 SlewF Test for DQ DM DQS Test Method of Implementation 86 SlewF Test for Address Control Clock Test Method of Implementation 88 SRQseR 40ohm Test Method of Implementa...

Page 72: ...t Application The channels shown in Figure 8 are just examples For more information on the probe amplifiers and differential probe heads see Chapter 20 InfiniiMax Probing starting on page 351 Test Procedure 1 Start the automated test application as described in Starting the DDR2 LP Compliance Test Application on page 27 2 Ensure that the RAM reliability test software is running on the computer sys...

Page 73: ...DR2 1066 7 Type in or select the Device Identifier as well as User Description from the drop down list Enter your comments in the Comments text box 8 Click the Select Tests tab and check the tests you want to run Check the parent node or group to check all the available tests within the group 9 Follow the DDR2 Test application s task flow to set up the configuration options run the tests and view ...

Page 74: ...set based on the different values of VPEAK The value of VDDQ which directly affects the conformance upper limit is set to 1 8V User may choose to use the UDL User Defined Limit feature in the application to perform this test against a customized test limit set based on the different values of VDDQ Signals of Interest Mode Supported DDR2 only Signal cycle of interest WRITE Signal s of Interest Data...

Page 75: ...of the acquired signal 2 Take the first valid WRITE burst found 3 Find all valid rising DQ crossings that cross VIH AC in the burst 4 For all DQ crossings found locate all the following DQS crossings that cross 0V 5 Calculate the time where the test result is taken Calculation is expressed as TTESTRESULT TDQS MIDPOINT tDS tDS DM and DQ input setup time in JEDEC specification which is due to speed ...

Page 76: ...it set based on the different values of VPEAK The value of VDDQ which directly affects the conformance upper limit is set to 1 8V User may choose to use the UDL User Defined Limit feature in the application to perform this test against a customized test limit set based on the different values of VDDQ Signals of Interest Mode Supported DDR2 only Signal cycle of interest WRITE Required Read Write se...

Page 77: ...of the acquired signal 2 Take the first valid WRITE burst found 3 Find all valid rising DQ crossings that cross VIH AC in the burst 4 For all DQ crossings found locate all the following DQS crossings that cross 0V 5 Calculate the time where the test result is taken Calculation is expressed as TTESTRESULT TDQS MIDPOINT tDS tDS DM and DQ input setup time in JEDEC specification which is due to speed ...

Page 78: ...st a customized test limit set based on the different values of VPEAK The value of VDDQ which directly affects the conformance upper limit is set to 1 8V User may choose to use the UDL User Defined Limit feature in the application to perform this test against a customized test limit set based on the different values of VDDQ Signals of Interest Mode Supported DDR2 only Signal cycle of interest WRIT...

Page 79: ...data 2 Find all valid positive pulses A valid positive pulse starts at VREF crossing at valid rising edge and end at VREF crossing at the following valid falling edge See notes on threshold 3 Zoom in on the first valid positive pulse and perform VTOP measurement Take the VTOP measurement results as VIH AC value 4 Continue the previous step with another 9 valid positive pulses that were found in th...

Page 80: ... 8V User may choose to use the UDL User Defined Limit feature in the application to perform this test against a customized test limit set based on the different values of VDDQ Signals of Interest Mode Supported DDR2 only Signal cycle of interest WRITE Required Read Write separation Yes Signal s of Interest Data Signals supported by Data Strobe Signals OR Data Mask Signals supported by Data Strobe ...

Page 81: ...For all DQ crossings found locate all the following DQS crossings that cross midpoint 0V for differential DQS and VREF for single ended DQS 5 Setup the histogram function settings where the X region is Ax X time position where tDS DM and DQ input setup time in JEDEC specification before DQS crossing midpoint Bx X time position where tDH DM and DQ input hold time in JEDEC specification after DQS cr...

Page 82: ...formance upper limit is set to 1 8V User may choose to use the UDL User Defined Limit feature in the application to perform this test against a customized test limit set based on the different values of VDDQ Signals of Interest Mode Supported DDR2 only Signal cycle of interest WRITE Required Read Write separation Yes Signal s of Interest Data Strobe Signals supported by Data Signals Signals requir...

Page 83: ...ind all valid Strobe positive pulse in the said burst A valid Strobe positive pulse starts at Vref crossing at valid Strobe rising edge See notes on threshold and end at Vref crossing at following valid Strobe falling edge See notes on threshold 4 For valid Strobe positive pulse 1 zoom on the pulse so that it appears on oscilloscope main screen and perform VTOP measurement Take result from VTOP me...

Page 84: ...ly affects the conformance upper limit is set to 1 8V User may choose to use the UDL User Defined Limit feature in the application to perform this test against a customized test limit set based on the different values of VDDQ Signals of Interest Mode Supported DDR2 only Signal cycle of interest WRITE Required Read Write separation No Signal s of Interest Address Signals OR Control Signals OR Clock...

Page 85: ...ata 2 Find all valid positive pulses A valid positive pulse starts at VREF crossing at a valid rising edge and ends at VREF crossing at the following valid falling edge See notes on threshold 3 Zoom in on the first valid positive pulse and perform VTOP measurement Take the VTOP measurement results as VIH DC value 4 Continue the previous step with another 9 valid positive pulses that were found in ...

Page 86: ...fects the conformance upper limit is set to 1 8V User may choose to use the UDL User Defined Limit feature in the application to perform this test against a customized test limit set based on the different values of VDDQ The value of VSSQ which directly affect the conformance upper limit is set to 0V User may choose to use the UDL User Defined Limit feature in the application to perform this test ...

Page 87: ...e and split read and write burst of the acquired signal 2 Take the first valid WRITE burst found 3 Find all valid falling DQ crossings that cross VIL AC in the burst 4 For all DQ crossings found locate all the following DQS crossings that cross Midpoint 0V for differential DQS and VREF for single ended DQS 5 Calculate the time where the test result is taken Calculation is expressed as TTESTRESULT ...

Page 88: ...Q which directly affects the conformance upper limit is set to 1 8V User may choose to use the UDL User Defined Limit feature in the application to perform this test against a customized test limit set based on the different values of VDDQ The value of VSSQ which directly affect the conformance upper limit is set to 0V User may choose to use the UDL User Defined Limit feature in the application to...

Page 89: ... write separation 2 Take the first valid WRITE burst found 3 Find all valid Strobe negative pulse in the said burst A valid Strobe negative pulse starts at Vref crossing at valid Strobe falling edge See notes on threshold and end at Vref crossing at following valid Strobe rising edge See notes on threshold 4 For valid Strobe negative pulse 1 zoom on the pulse so that it appears on oscilloscope mai...

Page 90: ...value of VDDQ which directly affects the conformance upper limit is set to 1 8V User may choose to use the UDL User Defined Limit feature in the application to perform this test against a customized test limit set based on the different values of VDDQ The value of VSSQ which directly affect the conformance upper limit is set to 0V User may choose to use the UDL User Defined Limit feature in the ap...

Page 91: ...or equal to the maximum VIL AC value Measurement Algorithm 1 Sample acquire signal data 2 Find all valid negative pulses A valid negative pulse starts at VREF crossing at a valid falling edge and ends at VREF crossing at the following rising valid edge See notes on threshold 3 Zoom in on the first valid negative pulse and perform VBASE measurement Take the VBASE measurement results as VIL AC value...

Page 92: ...ed test limit set based on the different values of VREF Signals of Interest Mode Supported DDR2 only Signal cycle of interest WRITE Required Read Write separation Yes Signal s of Interest Data Signals supported by Data Strobe Signals OR Data Mask Signals supported by Data Signals Signals required to perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined above Sup...

Page 93: ...r all DQ crossings found locate all the following DQS crossings that cross midpoint 0V for differential DQS and VREF for single ended DQS 5 Setup the histogram function settings where the X region is Ax X time position where tDS DM and DQ input setup time in JEDEC specification before DQS crossing midpoint Bx X time position where tDH DM and DQ input hold time in JEDEC specification after DQS cros...

Page 94: ...m this test against a customized test limit set based on the different values of VREF Signals of Interest Mode Supported DDR2 only Signal cycle of interest WRITE Required Read Write separation Yes Signal s of Interest Data Strobe Signal supported by Data Signal Signals required to perform the test on the oscilloscope Pin Under Test PUT Data Strobe Signals Supporting Pin Data Signals Test Definitio...

Page 95: ...nd all valid Strobe negative pulse in the said burst A valid Strobe negative pulse starts at Vref crossing at valid Strobe falling edge See notes on threshold and end at Vref crossing at following valid Strobe rising edge See notes on threshold 4 For valid Strobe negative pulse 1 zoom on the pulse so that it appears on oscilloscope main screen and perform VBASE measurement Take result from VBASE m...

Page 96: ...application to perform this test against a customized test limit set based on the different values of VREF Signals of Interest Mode Supported DDR2 only Signal cycle of interest WRITE Required Read Write separation No Signal s of Interest Address Signal OR Control Signal OR Clock Signal Signals required to perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined abo...

Page 97: ...ple acquire signal data 2 Find all valid negative pulses A valid negative pulse starts at VREF crossing at valid falling edge and end at VREF crossing at the following rising valid edge See notes on threshold 3 Zoom in on the first valid negative pulse and perform VBASE measurement Take the VBASE measurement results as VIL DC value 4 Continue the previous step with another nine valid negative puls...

Page 98: ...ITE Required Read Write separation Yes Signal s of Interest Data Signal supported by Data Strobe Signal OR Data Strobe Signal supported by Data Signal OR Data Mask Signal supported by Data Strobe Signal Signals required to perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined above Supporting Pin Data Strobe Signals if PUT is DQ DM Else Data Signals if PUT is DQ...

Page 99: ...ment Algorithm 1 Acquire and split read and write burst of the acquired signal See notes on DDR read write separation 2 Take the first valid WRITE burst found 3 Find all valid DQ DM DQS rising edges in the burst A valid rising edge starts at VIL AC crossing and ends at the following VIH AC crossing 4 For all valid rising edges find the transition time delta TR which is the time starting at VREF cr...

Page 100: ...d in the JEDEC specification Signals of Interest Mode Supported DDR2 only Signal cycle of interest WRITE Required Read Write separation No Signal s of Interest Address Signal OR Control Signal OR Clock Signal Signals required to perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined above Test Definition Notes from the Specification Table 53 AC Input Test Conditi...

Page 101: ...al should be greater than or equal to the SLEW value Measurement Algorithm 1 Acquire the signal 2 Find all valid rising edges in the whole acquisition A valid rising edge starts at VIL AC crossing and ends at the following VIH AC crossing 3 For all valid rising edges find the transition time delta TR which is the time starting at VREF crossing and ending at the following VIH AC crossing 4 Calculat...

Page 102: ...RITE Required Read Write separation Yes Signal s of Interest Data Signal supported by Data Strobe Signal OR Data Strobe Signal supported by Data Signal OR Data Mask Signal supported by Data Strobe Signal Signals required to perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined above Supporting Pin Data Strobe Signals if PUT is DQ DM Else Data Signals if PUT is D...

Page 103: ...ement Algorithm 1 Acquire and split read and write burst of the acquired signal See notes on DDR read write separation 2 Take the first valid WRITE burst found 3 Find all valid DQ DM DQS falling edges in the burst A valid falling edge starts at VIH AC crossing and ends at the following VIL AC crossing 4 For all valid falling edges find the transition time delta TR which is time starting at VREF cr...

Page 104: ...ed in the JEDEC specification Signals of Interest Mode Supported DDR2 only Signal cycle of interest WRITE Required Read Write separation No Signal s of Interest Address Signal OR Control Signal OR Clock Signal Signals required to perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined above Test Definition Notes from the Specification Table 57 AC Input Test Condit...

Page 105: ...al should be greater than or equal to the SLEW value Measurement Algorithm 1 Acquire the signal 2 Find all valid falling edges in the whole acquisition A valid falling edge starts at VIH AC crossing and ends at the following VIL AC crossing 3 For all valid rising edges find the transition time delta TR which is the time starting at VREF crossing and ending at the following VIL AC crossing 4 Calcul...

Page 106: ...se value as specified in the JEDEC specification Signals of Interest Mode Supported LPDDR2 only Signal cycle of interest READ Signal s of Interest Data Signal supported by Data Strobe Signal OR Data Strobe Signal supported by Data Signal Signals required to perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined above Supporting Pin Test Definition Notes from the ...

Page 107: ... burst found 3 Find all valid signal rising edges in this burst A valid signal rising edge starts at the VOL AC crossing and ends at the following VOH AC crossing 4 For all valid signal rising edges find the transition time TR which is the time that starts at the VOL AC crossing and ends at the following VOH AC crossing Then calculate SRQseR VOH AC VOL AC TR 5 Determine the worst result from the s...

Page 108: ...rting Pin Test Definition Notes from the Specification Test References See Table 85 Output Slew Rate single ended in the JESD209 2B PASS Condition The worst measured SRQseF shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write bursts of the acquired signal 2 Take the first valid READ burst found 3 Find all valid signal falling edges in this burst A valid ...

Page 109: ...rting Pin Test Definition Notes from the Specification Test References See Table 85 Output Slew Rate single ended in the JESD209 2B PASS Condition The worst measured SRQseR shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write bursts of the acquired signal 2 Take the first valid READ burst found 3 Find all valid signal rising edges in this burst A valid s...

Page 110: ...rting Pin Test Definition Notes from the Specification Test References See Table 85 Output Slew Rate single ended in the JESD209 2B PASS Condition The worst measured SRQseF shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write bursts of the acquired signal 2 Take the first valid READ burst found 3 Find all valid signal falling edges in this burst A valid ...

Page 111: ... any signal of interest as defined above Supporting Pin Test Definition Notes from the Specification Test References See Table 82 Single ended AC and DC Output Levels in the JESD209 2B PASS Condition The worst measured VOH AC shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write bursts of the acquired signal 2 Take the first valid READ burst found 3 Find ...

Page 112: ...ny signal of interest as defined above Supporting Pin Test Definition Notes from the Specification Test References See Table 82 Single ended AC and DC Output Levels in the JESD209 2B PASS Condition The worst measured VOH DC shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write bursts of the acquired signal 2 Take the first valid READ burst found 3 Find al...

Page 113: ...UT any signal of interest as defined above Supporting Pin Test Definition Notes from the Specification Test References See Table 82 Output Slew Rate single ended in the JESD209 2B PASS Condition The worst measured VOL AC shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write bursts of the acquired signal 2 Take the first valid READ burst found 3 Find all v...

Page 114: ...T any signal of interest as defined above Supporting Pin Test Definition Notes from the Specification Test References See Table 82 Output Slew Rate single ended in the JESD209 2B PASS Condition The worst measured VOL DC shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write bursts of the acquired signal 2 Take the first valid READ burst found 3 Find all va...

Page 115: ...mentation 102 VIHCA DC Test Method of Implementation 104 VILCA AC Test Method of Implementation 105 VILCA DC Test Method of Implementation 106 This section provides the Methods of Implementation MOIs for Single Ended Signals VIH VIL Address Control tests using a Keysight 80000B or 90000A Series Infiniium oscilloscope recommended InfiniiMax 116xA or 113xA probe amplifiers differential solder in pro...

Page 116: ...f the DDR2 LP Compliance Test Application The channels shown in Figure 10 are just examples For more information on the probe amplifiers and differential probe heads see Chapter 20 InfiniiMax Probing starting on page 351 Test Procedure 1 Start the automated test application as described in Starting the DDR2 LP Compliance Test Application on page 27 2 Ensure that the RAM reliability test software i...

Page 117: ... LPDDR2 Speed Grades check the Low Power box 7 Type in or select the Device Identifier as well as User Description from the drop down list Enter your comments in the Comments text box 8 Click the Select Tests tab and check the tests you want to run Check the parent node or group to check all the available tests within the group 9 Follow the DDR2 LP Test application s task flow to set up the config...

Page 118: ...fined Limit feature in the application to perform this test against a customized test limit set based on different values of VREF Signals of Interest Mode Supported LPDDR2 only Signal cycle of interest WRITE Signal s of Interest Command Address Signals Chip Select Signals Signals required to perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined above Test Defini...

Page 119: ...d positive pulse starts at VREF crossing at valid rising edge and end at VREF crossing at the following valid falling edge See notes on threshold 3 Zoom in on the first valid positive pulse and perform VTOP measurement Take the VTOP measurement results as VIHCA AC value 4 Continue the previous step with another nine valid positive pulses 5 Determine the worst result from the set of VIHCA AC measur...

Page 120: ...Supported LPDDR2 only Signal cycle of interest WRITE Signal s of Interest Command Address Signals Chip Select Signals Signals required to perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined above Test Definition Notes from the Specification Test References See Table 74 Single ended AC and DC Input Levels for CA and CS_n Inputs in the JESD209 2B PASS Condition ...

Page 121: ...Chip Select Signals Signals required to perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined above Test Definition Notes from the Specification Test References See Table 74 Single ended AC and DC Input Levels for CA and CS_n Inputs in the JESD209 2B PASS Condition The mode value for the low level voltage must be less than or equal to the minimum VILCA AC value ...

Page 122: ...2 only Signal cycle of interest WRITE Signal s of Interest Command Address Signals Chip Select Signals Signals required to perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined above Test Definition Notes from the Specification Test References See Table 74 Single ended AC and DC Input Levels for CA and CS_n Inputs in the JESD209 2B PASS Condition The mode value ...

Page 123: ...tation 110 VIHDQ DC Test Method of Implementation 112 VILDQ AC Test Method of Implementation 114 VILDQ DC Test Method of Implementation 116 This section provides the Methods of Implementation MOIs for Single Ended Signals VIH VIL Data Mask tests using a Keysight 80000B or 90000A Series Infiniium oscilloscope recommended InfiniiMax 116xA or 113xA probe amplifiers differential solder in probe head a...

Page 124: ...2 LP Compliance Test Application The channels shown in Figure 12 are just examples For more information on the probe amplifiers and differential probe heads see Chapter 20 InfiniiMax Probing starting on page 351 Test Procedure 1 Start the automated test application as described in Starting the DDR2 LP Compliance Test Application on page 27 2 Ensure that the RAM reliability test software is running...

Page 125: ...DDR2 Speed Grades check the Low Power box 7 Type in or select the Device Identifier as well as User Description from the drop down list Enter your comments in the Comments text box 8 Click the Select Tests tab and check the tests you want to run Check the parent node or group to check all the available tests within the group 9 Follow the DDR2 LP Test application s task flow to set up the configura...

Page 126: ...zed test limit set based on different values of VREF Signals of Interest Mode Supported LPDDR2 only Signal cycle of interest WRITE Signal s of Interest Data Signals supported by Data Strobe Signals OR Data Mask Signals supported by Data Strobe Signals Signals required to perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined above Supporting Pin Data Strobe Signa...

Page 127: ...that cross VIH AC in the burst 4 For all DQ crossings found locate all the following DQS crossings that cross 0V 5 Calculate the time where the test result is taken Calculation is expressed as TTESTRESULT TDQS MIDPOINT tDS tDS DM and DQ input setup time in JEDEC specification which is due to speed grade 6 Take voltage level of DQ signal at TTESTRESULT as the test result for VIHDQ AC 7 Collect all ...

Page 128: ...fined Limit feature in the application to perform this test against a customized test limit set based on different values of VDDQ Signals of Interest Mode Supported LPDDR2 only Signal cycle of interest WRITE Signal s of Interest Data Signals supported by Data Strobe Signals OR Data Mask Signals supported by Data Strobe Signals Signals required to perform the test on the oscilloscope Pin Under Test...

Page 129: ...differential DQS and VREF is for single ended DQS 5 Set up histogram function settings Ax X time position where tDS DM and DQ input setup time in JEDEC specification before DQS crossing midpoint Bx X time position where tDH DM and DQ input hold time in JEDEC specification after DQS crossing midpoint Ay Top of the displaying window just to make sure it covers the maximum level of the respective sig...

Page 130: ...zed test limit set based on different values of VREF Signals of Interest Mode Supported LPDDR2 only Signal cycle of interest WRITE Signal s of Interest Data Signals supported by Data Strobe Signals OR Data Mask Signals supported by Data Strobe Signals Signals required to perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined above Supporting Pin Data Strobe Signa...

Page 131: ...For all DQ crossings found locate all the following DQS crossings that cross midpoint 0V is for differential DQS and VREF is for single ended DQS 5 Calculate the time where the test result is taken Calculation is expressed as TTESTRESULT TDQS MIDPOINT tDS tDS DM and DQ input setup time in JEDEC specification which is due to speed grade 6 Take voltage level of DQ signal at TTESTRESULT as the test r...

Page 132: ...fined Limit feature in the application to perform this test against a customized test limit set based on different values of VSSQ Signals of Interest Mode Supported LPDDR2 only Signal cycle of interest WRITE Signal s of Interest Data Signals supported by Data Strobe Signals OR Data Mask Signals supported by Data Strobe Signals Signals required to perform the test on the oscilloscope Pin Under Test...

Page 133: ...differential DQS and VREF is for single ended DQS 5 Set up histogram function settings Ax X time position where tDS DM and DQ input setup time in JEDEC specification before DQS crossing midpoint Bx X time position where tDH DM and DQ input hold time in JEDEC specification after DQS crossing midpoint Ay Top of the displaying window just to make sure it covers the maximum level of the respective sig...

Page 134: ...6 Single Ended Signals VIH VIL Data Mask Tests 118 DDR2 LP Compliance Testing Methods of Implementation ...

Page 135: ...Signals 120 VSEH AC strobe Test Method of Implementation 122 VSEL AC strobe Test Method of Implementation 124 This section provides the Methods of Implementation MOIs for Single Ended Signals AC parameter tests for Strobe Signals using a Keysight 80000B or 90000A Series Infiniium oscilloscope recommended InfiniiMax 116xA or 113xA probe amplifiers differential solder in probe head and the DDR2 LP C...

Page 136: ...guration tab of the DDR2 LP Compliance Test Application The channels shown in Figure 14 are just examples For more information on the probe amplifiers and differential probe heads see Chapter 20 InfiniiMax Probing starting on page 351 Test Procedure 1 Start the automated test application as described in Starting the DDR2 LP Compliance Test Application on page 27 2 Ensure that the RAM reliability t...

Page 137: ... the LPDDR2 Speed Grades check the Low Power box 7 Type in or select the Device Identifier as well as User Description from the drop down list Enter your comments in the Comments text box 8 Click the Select Tests tab and check the tests you want to run Check the parent node or group to check all the available tests within the group 9 Follow the DDR2 LP Test application s task flow to set up the co...

Page 138: ...e application to perform this test against a customized test limit set based on different values of VDDQ Signals of Interest Mode Supported LPDDR2 only Signal cycle of interest WRITE Signal s of Interest Data Strobe Signals supported by Data Signals Signals required to perform the test on the oscilloscope Pin Under Test PUT Data Strobe Signals Supporting Pin Data Signals Test Definition Notes from...

Page 139: ...REF crossing on a valid strobe rising edge and ends at the VREF crossing on the following valid strobe falling edge 4 For the first valid strobe positive pulse zoom in on the pulse so that it appears on the oscilloscope s display and perform TMAX Then perform VTIME at the found TMAX to get the maximum voltage of the pulse Take the VTIME measurement result as the VSEH AC value 5 Continue the previo...

Page 140: ...Table 79 Single ended Levels for CK_t DQS_t CK_c and DQS_c in the JESD209 2B PASS Condition The worst measured VSEL AC shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write bursts of the acquired signal 2 Take the first valid WRITE burst found 3 Find all valid strobe negative pulses in this burst A valid strobe negative pulse starts at the VREF crossing o...

Page 141: ...Method of Implementation 130 VIHCKE Test Input Logic High Clock Enable Test Method of Implementation 131 VILCKE Test Input Logic Low Clock Enable Test Method of Implementation 132 This section provides the Methods of Implementation MOIs for Single Ended Signals AC parameter tests for Clock using a Keysight 80000B or 90000A Series Infiniium oscilloscope recommended InfiniiMax 116xA or 113xA probe a...

Page 142: ...of the DDR2 LP Compliance Test Application The channels shown in Figure 16 are just examples For more information on the probe amplifiers and differential probe heads see Chapter 20 InfiniiMax Probing starting on page 351 Test Procedure 1 Start the automated test application as described in Starting the DDR2 LP Compliance Test Application on page 27 2 Ensure that the RAM reliability test software ...

Page 143: ... LPDDR2 Speed Grades check the Low Power box 7 Type in or select the Device Identifier as well as User Description from the drop down list Enter your comments in the Comments text box 8 Click the Select Tests tab and check the tests you want to run Check the parent node or group to check all the available tests within the group 9 Follow the DDR2 LP Test application s task flow to set up the config...

Page 144: ...efined Limit feature in the application to perform this test against a customized test limit set based on different values of VDDCA Signals of Interest Mode Supported LPDDR2 only Signal cycle of interest WRITE Signal s of Interest Clock Signals Signals required to perform the test on the oscilloscope Pin Under Test PUT Clock Signals Test Definition Notes from the Specification Test References See ...

Page 145: ...sing on a valid Clock rising edge and ends at the VREF crossing on the following valid Clock falling edge 4 For the first valid Clock positive pulse zoom in on the pulse so that it appears on the oscilloscope s display and perform TMAX Then perform VTIME at the found TMAX to get the maximum voltage of the pulse Take the VTIME measurement result as the VSEH AC value 5 Continue the previous step for...

Page 146: ...K_t DQS_t CK_c and DQS_c in the JESD209 2B PASS Condition The worst measured VSEL AC shall be within the specification limit Measurement Algorithm 1 Pre condition the oscilloscope 2 Trigger on a rising edge of the clock signal under test 3 Find all valid Clock negative pulses in the entire waveform A valid Clock negative pulse starts at the VREF crossing on a valid Clock falling edge and ends at t...

Page 147: ...s of Interest Clock Enable Signal Signals required to perform the test on the oscilloscope Pin Under Test PUT any of the signal of interest defined above Test Definition Notes from the Specification Test References See Table 75 Single ended AC and DC Input Levels for CKE in the JESD209 2B PASS Condition The mode value for the high level voltage shall be greater than or equal to the minimum VIHCKE ...

Page 148: ...l s of Interest Clock Enable Signal Signals required to perform the test on the oscilloscope Pin Under Test PUT any of the signal of interest defined above Test Definition Notes from the Specification Test References See Table 75 Single ended AC and DC Input Levels for CKE in the JESD209 2B PASS Condition The mode value for the low level voltage shall be less than or equal to the minimum VILCKE va...

Page 149: ...Overshoot Test Method of Implementation 136 AC Undershoot Test Method of Implementation 139 This section provides the Methods of Implementation MOIs for Single Ended Signals Overshoot Undershoot tests using a Keysight 80000B or 90000A Series Infiniium oscilloscope recommended InfiniiMax 116xA or 113xA probe amplifiers differential solder in probe head and the DDR2 LP Compliance Test Application ...

Page 150: ...20 InfiniiMax Probing starting on page 351 Test Procedure 1 Start the automated test application as described in Starting the DDR2 LP Compliance Test Application on page 27 2 Ensure that the RAM reliability test software is running on the computer system where the DDR2 LPDDR2 Device Under Test DUT is attached This software will perform test on all unused RAM on the system by producing repetitive b...

Page 151: ...own list Enter your comments in the Comments text box 8 Click the Select Tests tab and check the tests you want to run Check the parent node or group to check all the available tests within the group 9 Follow the DDR2 LP Test application s task flow to set up the configuration options run the tests and view the tests results Figure 19 Selecting Single Ended Signals Overshoot Undershoot Tests ...

Page 152: ...PDDR2 Signal cycle of interest READ or WRITE Signal s of Interest Data Signal OR Data Strobe Signal OR Address Signal OR Control Signal OR Data Mask Control Signal OR Clock Signal Signals required to perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined above Test Definition Notes from the Specification Table 81 AC Overshoot Specification for Address and Control...

Page 153: ...ck Data Strobe and Mask Pins DDR2 1066 DQ U L R DQS U L R DQS DM CK CK Parameter Specification DDR2 1066 Maximum peak amplitude allowed for overshoot area 0 5 V Maximum overshoot area above VDDQ 0 19 V ns Table 85 LPDDR2 AC Overshoot Undershoot Specification Parameter 1066 933 800 677 533 466 400 333 266 200 Unit Maximum peak amplitude allowed for overshoot area Max 0 35 V Maximum peak amplitude a...

Page 154: ...es 2 Sample acquire signal data and perform signal conditioning to maximize the screen resolution vertical scale adjustment 3 Use TMAX VMAX to get a timestamp of the maximum voltage on all regions of acquired waveform 4 Perform manual zoom on waveform to maximize peak area 5 Find the edges before and after the Overshoot Point at the Supply Reference Level in order to calculate the maximum overshoo...

Page 155: ... LPDDR2 Signal cycle of interest READ or WRITE Signal s of Interest Data Signal OR Data Strobe Signal OR Address Signal OR Control Signal OR Data Mask Control Signal OR Clock Signal Signals required to perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined above Test Definition Notes from the Specification Table 86 AC Undershoot Specification for Address and Cont...

Page 156: ...ock Data Strobe and Mask Pins DDR2 1066 DQ U L R DQS U L R DQS DM CK CK Parameter Specification DDR2 1066 Maximum peak amplitude allowed for undershoot area 0 5 V Maximum undershoot area below VSSQ 0 19 V ns Table 90 LPDDR2 AC Overshoot Undershoot Specification Parameter 1066 933 800 677 533 466 400 333 266 200 Unit Maximum peak amplitude allowed for overshoot area Max 0 35 V Maximum peak amplitud...

Page 157: ... undershoot area value should be less than or equal to the maximum undershoot area allowed Measurement Algorithm 1 Set the number of sampling points to 2M samples 2 Sample acquire signal data and perform signal conditioning to maximize the screen resolution vertical scale adjustment 3 Use TMAX VMAX to get a timestamp of the minimum voltage on all regions of acquired waveform 4 Perform manual zoom ...

Page 158: ...9 Single Ended Signals Overshoot Undershoot Tests 142 DDR2 LP Compliance Testing Methods of Implementation ...

Page 159: ...on 152 VIHdiff AC Test for DQS Test Method of Implementation 154 VIHdiff AC Test for Clock Test Method of Implementation 156 VIHdiff DC Test for DQS Test Method of Implementation 158 VIHdiff DC Test for Clock Test Method of Implementation 160 VILdiff AC Test for DQS Test Method of Implementation 162 VILdiff AC Test for Clock Test Method of Implementation 164 VILdiff DC Test for DQS Test Method of ...

Page 160: ...nnels shown in Figure 20 are just examples For more information on the probe amplifiers and differential probe heads see Chapter 20 InfiniiMax Probing starting on page 351 Test Procedure 1 Start the automated test application as described in Starting the DDR2 LP Compliance Test Application on page 27 2 Ensure that the RAM reliability test software is running on the computer system where the DDR2 L...

Page 161: ...ort LPDDR2 check the Low Power box 7 Type in or select the Device Identifier as well as User Description from the drop down list Enter your comments in the Comments text box 8 Click the Select Tests tab and check the tests you want to run Check the parent node or group to check all the available tests within the group 9 Follow the DDR2 LP Test application s task flow to set up the configuration op...

Page 162: ...L User Defined Limit feature in the application to perform this test against a customized test limit set based on different values of VDDQ Signals of Interest Mode Supported DDR2 only Signal cycle of interest WRITE Require Read Write separation Yes Signal s of Interest Data Strobe Signal supported by Data Signal Signals required to perform the test on the oscilloscope Pin Under Test PUT Data Strob...

Page 163: ...quire data waveforms 2 Use Subtract FUNC to generate the differential waveform from the two source inputs 3 Split read and write burst of the acquired signal 4 Take the first valid WRITE burst found 5 Find all differential DQS crossing that cross 0V 6 Within the first and second DQS crossing regions perform VTOP on DQS Gnd or DQS Gnd depending on which one is the positive pulse in current region N...

Page 164: ...sed User may choose to use the UDL User Defined Limit feature in the application to perform this test against a customized test limit set based on different values of VDDQ Signals of Interest Mode Supported DDR2 only Signal cycle of interest WRITE Require Read Write separation NO Signal s of Interest Clock Signals Signals required to perform the test on the oscilloscope Pin Under Test PUT Clock Si...

Page 165: ...Algorithm 1 Sample acquire data waveforms 2 Use Subtract FUNC to generate the differential waveform from the two source inputs 3 Find the first 10 differential CLK crossing that cross 0V 4 Within first and second CLK crossing region perform VTOP on CLK GND OR CLK GND depending on which one is the positive pulse in the current region Next perform VBASE on CLK GND OR CLK GND depending on which one i...

Page 166: ...in the application to perform this test against a customized test limit set based on different values of VDDQ Signals of Interest Mode Supported DDR2 only Signal cycle of interest WRITE Required Read Write separation Yes Signal s of Interest Data Strobe Signal supported by Data Signal Signals required to perform the test on the oscilloscope Pin Under Test PUT Data Strobe Signals Supporting Pin Dat...

Page 167: ...e differential test signals pair should be within the conformance limits of VIX AC value Measurement Algorithm 1 Sample acquire data waveforms 2 Use Subtract FUNC to generate the differential waveform from the two source inputs 3 Split read and write bursts of the acquired signal 4 Take the first valid WRITE burst found 5 Find all differential DQS crossing that cross 0V 6 Use VTime to get the actu...

Page 168: ...he UDL User Defined Limit feature in the application to perform this test against a customized test limit set based on different values of VDDQ Signals of Interest Mode Supported DDR2 only Signal cycle of interest WRITE Required Read Write separation No Signal s of Interest Clock Signals Signals required to perform the test on the oscilloscope Pin Under Test PUT Clock Signals Test Definition Notes...

Page 169: ... The measured crossing point value for the differential test signals pair should be within the conformance limits of VIX AC value Measurement Algorithm 1 Sample acquire data waveforms 2 Use Subtract FUNC to generate the differential waveform from the two source inputs 3 Find the first 10 differential CLK crossing that cross 0V 4 Use VTime to get the actual crossing point voltage value by using the...

Page 170: ...DDR2 200 to LPDDR2 400 or 0 82V for Speed Grades from LPDDR2 466 to LPDDR2 1066 for the compliance limit set used User may choose to use the UDL User Defined Limit feature in the application to perform this test against a customized test limit set based on different values of VIH DC Signals of Interest Mode Supported LPDDR2 only Signal cycle of interest WRITE Required Read Write separation Yes Sig...

Page 171: ...pulse starts at 0 Volt crossing at valid Strobe rising edge see notes on threshold and ends at the 0V crossing on the following valid Strobe falling edge see notes on threshold 4 For the first valid Strobe positive pulse zoom in on the pulse so that it appears on the oscilloscope s display and perform the VTOP measurement Take the VTOP measurement result as the VIHdiff AC value 5 Continue the prev...

Page 172: ...et to 0 9V for Speed Grades from LPDDR2 200 to LPDDR2 400 or 0 82V for Speed Grades from LPDDR2 466 to LPDDR2 1066 for the compliance limit set used User may choose to use the UDL User Defined Limit feature in the application to perform this test against a customized test limit set based on different values of VIH DC Signals of Interest Mode Supported LPDDR2 only Signal cycle of interest WRITE Req...

Page 173: ...starts at the 0V crossing on a valid Clock rising edge see notes on threshold and ends at the 0V crossing on the following valid Clock falling edge see notes on threshold 4 For the first valid Clock positive pulse zoom in on the pulse so that it appears on the oscilloscope s display and perform the VTOP measurement Take the VTOP measurement result as the VIHdiff AC value 5 Continue the previous st...

Page 174: ...DDR2 200 to LPDDR2 400 or 0 73V for Speed Grades from LPDDR2 466 to LPDDR2 1066 for the compliance limit set used User may choose to use the UDL User Defined Limit feature in the application to perform this test against a customized test limit set based on different values of VIH DC Signals of Interest Mode Supported LPDDR2 only Signal cycle of interest WRITE Required Read Write separation Yes Sig...

Page 175: ...ositive pulse starts at the 0V crossing on a valid Strobe rising edge see notes on threshold and ends at the 0V crossing on the following valid Strobe falling edge see notes on threshold 4 For the first valid Strobe positive pulse zoom in on the pulse so that it appears on the oscilloscope s display and perform the VTOP measurement Take the VTOP measurement result as the VIHdiff DC value 5 Continu...

Page 176: ...set to 0 8V for Speed Grades from LPDDR2 200 to LPDDR2 400 or 0 73V for Speed Grades from LPDDR2 466 to LPDDR2 1066 for the compliance limit set used User may choose to use the UDL User Defined Limit feature in the application to perform this test against a customized test limit set based on different values of VIH DC Signals of Interest Mode Supported LPDDR2 only Signal cycle of interest WRITE Re...

Page 177: ...starts at the 0V crossing on a valid Clock rising edge see notes on threshold and ends at the 0V crossing on the following valid Clock falling edge see notes on threshold 4 For the first valid Clock positive pulse zoom in on the pulse so that it appears on the oscilloscope s display and perform the VTOP measurement Take the VTOP measurement result as the VIHdiff DC value 5 Continue the previous st...

Page 178: ...DR2 200 to LPDDR2 400 or 0 38V for Speed Grades from LPDDR2 466 to LPDDR2 1066 for the compliance limit set used User may choose to use the UDL User Defined Limit feature in the application to perform this test against a customized test limit set based on different values of VIH DC Signals of Interest Mode Supported LPDDR2 only Signal cycle of interest WRITE Required Read Write separation Yes Sign...

Page 179: ...gative pulse starts at the 0V crossing on a valid Strobe falling edge see notes on threshold and ends at the 0V crossing on the following valid Strobe rising edge see notes on threshold 4 For the first valid Strobe negative pulse zoom in on the pulse so that it appears on the oscilloscope s display and perform the VBASE measurement Take the VBASE measurement result as the VILdiff AC value 5 Contin...

Page 180: ...et to 0 3V for Speed Grades from LPDDR2 200 to LPDDR2 400 or 0 38V for Speed Grades from LPDDR2 466 to LPDDR2 1066 for the compliance limit set used User may choose to use the UDL User Defined Limit feature in the application to perform this test against a customized test limit set based on different values of VIH DC Signals of Interest Mode Supported LPDDR2 only Signal cycle of interest WRITE Req...

Page 181: ...starts at the 0V crossing on a valid Clock falling edge see notes on threshold and ends at the 0V crossing on the following valid Clock rising edge see notes on threshold 4 For the first valid Clock negative pulse zoom in on the pulse so that it appears on the oscilloscope s display and perform the VBASE measurement Take the VBASE measurement result as the VILdiff AC value 5 Continue the previous ...

Page 182: ...DDR2 200 to LPDDR2 400 or 0 47V for Speed Grades from LPDDR2 466 to LPDDR2 1066 for the compliance limit set used User may choose to use the UDL User Defined Limit feature in the application to perform this test against a customize test limit set based on different values of VIH DC Signals of Interest Mode Supported LPDDR2 only Signal cycle of interest WRITE Required Read Write separation Yes Sign...

Page 183: ...gative pulse starts at the 0V crossing on a valid Strobe falling edge see notes on threshold and ends at the 0V crossing on the following valid Strobe rising edge see notes on threshold 4 For the first valid Strobe negative pulse zoom in on the pulse so that it appears on the oscilloscope s display and perform the VBASE measurement Take the VBASE measurement result as the VILdiff DC value 5 Contin...

Page 184: ...set to 0 4V for Speed Grades from LPDDR2 200 to LPDDR2 400 or 0 47V for Speed Grades from LPDDR2 466 to LPDDR2 1066 for the compliance limit set used User may choose to use the UDL User Defined Limit feature in the application to perform this test against a customize test limit set based on different values of VIH DC Signals of Interest Mode Supported LPDDR2 only Signal cycle of interest WRITE Req...

Page 185: ...tarts at the 0Volt crossing on a valid Clock falling edge see notes on threshold and ends at the 0V crossing on the following valid Clock rising edge see notes on threshold 4 For the first valid Clock negative pulse zoom in on the pulse so that it appears on the oscilloscope s display and perform the VBASE measurement Take the VBASE measurement result as the VILdiff DC value 5 Continue the previou...

Page 186: ...10 Differential Signals AC Input Parameters Tests 170 DDR2 LP Compliance Testing Methods of Implementation ...

Page 187: ...on 176 SRQdiffF 40ohm Test Method of Implementation 178 SRQdiffR 60ohm Test Method of Implementation 179 SRQdiffF 60ohm Test Method of Implementation 180 VOHdiff AC Test Method of Implementation 181 VOLdiff AC Test Method of Implementation 182 This section provides the Methods of Implementation MOIs for Differential Signals AC Output tests using a Keysight 80000B or 90000A Series Infiniium oscillo...

Page 188: ...nnels shown in Figure 22 are just examples For more information on the probe amplifiers and differential probe heads see Chapter 20 InfiniiMax Probing starting on page 351 Test Procedure 1 Start the automated test application as described in Starting the DDR2 LP Compliance Test Application on page 27 2 Ensure that the RAM reliability test software is running on the computer system where the DDR2 L...

Page 189: ...he Low Power box 7 Type in or select the Device Identifier as well as User Description from the drop down list Enter your comments in the Comments text box 8 Click the Select Tests tab and check the tests you want to run Check the parent node or group to check all the available tests within the group 9 Follow the DDR2 LP Test application s task flow to set up the configuration options run the test...

Page 190: ...is test against a customized test limit set based on the different values of VDDQ Signals of Interest Mode Supported DDR2 only Signal cycle of interest READ Signal s of Interest Data Strobe Signal supported by Data Signal Signals required to perform the test on the oscilloscope Pin Under Test PUT any signal of interest as defined above Supporting Pin a corresponding DQ signal Test Definition Notes...

Page 191: ...erential test signals pair should be within the conformance limits of VOX AC value Measurement Algorithm 1 Obtain sample or acquire data waveforms 2 Use Subtract FUNC to generate the differential waveform from the two source inputs 3 Split read and write bursts of the acquired signal 4 Take the first valid READ burst found 5 Find all differential DQS crossings that cross 0V 6 Use VTIME to get the ...

Page 192: ...mance limit of the SRQdiff value as specified in the JEDEC specification Signals of Interest Mode Supported LPDDR2 only Signal cycle of interest READ Signal s of Interest Data Strobe Signal supported by Data Signal Signals required to perform the test on the oscilloscope Pin Under Test PUT Data Strobe Signals Supporting Pin Data Signals Test Definition Notes from the Specification Test References ...

Page 193: ...3 Find all valid Strobe rising edges in this burst A valid Strobe rising edge starts at the VOLdiff AC crossing and ends at the following VOHdiff AC crossing 4 For all valid Strobe rising edges find the transition time TR which is the time that starts at the VOLdiff AC crossing and ends at the following VOHdiff AC crossing Then calculate SRQdiffR VOHdiff AC VOLdiff AC TR 5 Determine the worst resu...

Page 194: ... Specification Test References See Table 87 Output Slew Rate differential in the JESD209 2B PASS Condition The worst measured SRQdiffF shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write bursts of the acquired signal 2 Take the first valid READ burst found 3 Find all valid Strobe falling edges in this burst A valid Strobe falling edge starts at the VOHd...

Page 195: ...e Specification Test References See Table 87 Output Slew Rate differential in the JESD209 2B PASS Condition The worst measured SRQdiffR shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write bursts of the acquired signal 2 Take the first valid READ burst found 3 Find all valid Strobe rising edges in this burst A valid Strobe rising edge starts at the VOLdi...

Page 196: ... Specification Test References See Table 87 Output Slew Rate differential in the JESD209 2B PASS Condition The worst measured SRQdiffF shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write bursts of the acquired signal 2 Take the first valid READ burst found 3 Find all valid Strobe falling edges in this burst A valid Strobe falling edge starts at the VOHd...

Page 197: ...pporting Pin Data Signals Test Definition Notes from the Specification Test References See Table 83 Differential AC and DC Output Levels in the JESD209 2B PASS Condition The worst measured VOHdiff AC shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write bursts of the acquired signal 2 Take the first valid READ burst found 3 Find all valid Strobe positive ...

Page 198: ...porting Pin Data Signals Test Definition Notes from the Specification Test References See Table 83 Differential AC and DC Output Levels in the JESD209 2B PASS Condition The worst measured VOLdiff AC shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write bursts of the acquired signal 2 Take the first valid READ burst found 3 Find all valid Strobe negative p...

Page 199: ... Point Voltage Tests 184 VIXCA Clock Cross Point Voltage Test Method of Implementation 186 This section provides the Methods of Implementation MOIs for Differential Signals Clock Cross Point Voltage tests using a Keysight 80000B or 90000A Series Infiniium oscilloscope recommended InfiniiMax 116xA or 113xA probe amplifiers differential solder in probe head and the DDR2 LP Compliance Test Applicatio...

Page 200: ...ion The channels shown in Figure 24 are just examples For more information on the probe amplifiers and differential probe heads see Chapter 20 InfiniiMax Probing starting on page 351 Test Procedure 1 Start the automated test application as described in Starting the DDR2 LP Compliance Test Application on page 27 2 Ensure that the RAM reliability test software is running on the computer system where...

Page 201: ...the Low Power box 7 Type in or select the Device Identifier as well as User Description from the drop down list Enter your comments in the Comments text box 8 Click the Select Tests tab and check the tests you want to run Check the parent node or group to check all the available tests within the group Follow the DDR2 LP Test application s task flow to set up the configuration options run the tests...

Page 202: ... References See Table 80 Cross Point Voltage for Differential Input Signals CK DQS in the JESD209 2B PASS Condition The measured crossing point value for the differential Clock signals pair should be within the conformance limits of VIXCA value Measurement Algorithm 1 Obtain sample or acquire data waveforms 2 Use Subtract FUNC to generate the differential waveform from the two source inputs 3 Find...

Page 203: ... Point Voltage Tests 188 VIXDQ Strobe Cross Point Voltage Test Method of Implementation 190 This section provides the Methods of Implementation MOIs for Differential Signals Strobe Cross Point Voltage tests using a Keysight 80000B or 90000A Series Infiniium oscilloscope recommended InfiniiMax 116xA or 113xA probe amplifiers differential solder in probe head and the DDR2 LP Compliance Test Applicat...

Page 204: ...ation The channels shown in Figure 26 are just examples For more information on the probe amplifiers and differential probe heads see Chapter 20 InfiniiMax Probing starting on page 351 Test Procedure 1 Start the automated test application as described in Starting the DDR2 LP Compliance Test Application on page 27 2 Ensure that the RAM reliability test software is running on the computer system whe...

Page 205: ... the Low Power box 7 Type in or select the Device Identifier as well as User Description from the drop down list Enter your comments in the Comments text box 8 Click the Select Tests tab and check the tests you want to run Check the parent node or group to check all the available tests within the group Follow the DDR2 LP Test application s task flow to set up the configuration options run the test...

Page 206: ...ces See Table 80 Cross Point Voltage for Differential Input Signals CK DQS in the JESD209 2B PASS Condition The measured crossing point value for the differential Clock signals pair should be within the conformance limits of VIXDQ value Measurement Algorithm 1 Obtain sample or acquire data waveforms 2 Use Subtract FUNC to generate the differential waveform from the two source inputs 3 Split read a...

Page 207: ... VIHdiff AC Below VILdiff AC Test Method of Implementation 200 tQHS Data Hold Skew Factor Test Method of Implementation 202 tDQSCKDS Test DQSCK Delta Short Test Test Method of Implementation 204 tDQSCKDM Test DQSCK Delta Medium Test Test Method of Implementation 206 This section provides the Methods of Implementation MOIs for Clock Timing tests using a Keysight 80000B or 90000A Series Infiniium os...

Page 208: ...e amplifiers and differential probe heads see Chapter 20 InfiniiMax Probing starting on page 351 Test Procedure 1 Start the automated test application as described in Starting the DDR2 LP Compliance Test Application on page 27 2 Ensure that the RAM reliability test software is running on the computer system where the DDR2 Device Under Test DUT is attached This software will perform test on all the...

Page 209: ...p down list Enter your comments in the Comments text box 8 Click the Select Tests tab and check the tests you want to run Check the parent node or group to check all the available tests within the group 9 Follow the DDR2 Test application s task flow to set up the configuration options run the tests and view the tests results Figure 29 Selecting Clock Timing Tests ...

Page 210: ...on the oscilloscope Data Signal DQ Data Strobe Signal DQS Clock Signal CK Chip Select Signal CS optional Test Definition Notes from the Specification Test References See Table 41 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 and Table 42 Timing Parameters by Speed Grade DDR2 667 and DDR2 800 in the JEDEC Standard JESD79 2E Also see Table 41 Timing Parameters by Speed Grade DDR2 1066 in th...

Page 211: ... the oscilloscope setting 2 Acquire and split read and write burst of the acquired signal 3 Take the first valid READ burst found 4 Find all valid rising and falling DQ crossings at Vref in the said burst 5 For all DQ crossings found locate the nearest rising Clock crossing at 0V 6 Take the time difference from DQ crossing to the corresponding Clock crossing as the tAC 7 Determine the worst result...

Page 212: ...to perform the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Clock Signal CK Chip Select Signal CS optional Test Definition Notes from the Specification Test References See Table 41 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 and Table 42 Timing Parameters by Speed Grade DDR2 667 and DDR2 800 in the JEDEC Standard JESD79 2E Also see Table 41 Timing Parameters by Speed G...

Page 213: ...e setting 2 Acquire and split read and write burst of the acquired signal 3 Take the first valid READ burst found 4 Find all valid rising and falling DQS crossings at Vref in the said burst 5 For all DQS crossings found locate the nearest rising Clock crossing at 0V 6 Take the time difference from DQS crossing to the corresponding Clock crossing as the tDQSCK 7 Determine the worst result from the ...

Page 214: ...tDQSCK Test Signal s of Interest Data Strobe Signal supported by Data Signal Clock Signal CK as Reference Signal Optional signal s Chip Select Signal this signal is used to separate DQS signals from different rank of memory Signals required to perform the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Clock Signal CK Chip Select Signal CS optional Test Definition Notes from the Spe...

Page 215: ...ge 7 Find the tDQSCK clock point It is the Clock middle crossing point right before the closest Clock DQS at tDQSCK Delay cycle By default tDQSCK Delay is one cycle For example if tDQSCK Delay 1 then the tDQSCK clock point is the Clock middle crossing point right before the closest Clock DQS If tDQSCK Delay 3 then the tDQSCK clock point is the Clock middle crossing point three clock cycles before ...

Page 216: ...d LPDDR2 Signal s of Interest Clock Signal Signals required to perform the test on the oscilloscope Clock Signal CK Test Definition Notes from the Specification Test References See Table 78 Allowed Time Before Ringback tDVAC for CK_t CK_s and DQS_t DQS_c in the JESD209 2B PASS Condition The worst measured tDVAC Clock should be within the specification limit Table 122 Allowed time before ringback t...

Page 217: ... interval starting from a rising VIHdiff AC crossing point and ending at the following falling VIHdiff AC crossing point 6 tDVAC Clock is also the time interval starting from a falling VILdiff AC crossing point and ending at the following rising VILdiff AC crossing point 7 Collect all tDVAC Clock results 8 Determine the worst result from the set of tDVAC Clock measured 9 Report the worst result fr...

Page 218: ...ted by Data Strobe Signal Clock Signal CK as Reference Signal Optional signal s Chip Select Signal this signal is used to separate DQS signals from different rank of memory Signals required to perform the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Clock Signal CK Chip Select Signal CS optional Test Definition Notes from the Specification Test References See Table 103 LPDDR2 AC ...

Page 219: ...d write separation 2 Take the first valid READ burst found 3 Find all valid rising and falling DQ crossings at VREF in the said burst See notes on threshold 4 For all DQ crossings found locate the nearest DQS crossing Rising and falling See notes on threshold 5 Take the time different from DQS crossing to DQ crossing as the tQHS 6 Determine the worst result from the set of tQHS measured ...

Page 220: ... Signal cycle of interest READ Mode Supported LPDDR2 Required Read Write separation Yes Signal s of Interest Data Strobe Signals supported by Data Signal Clock Signal CK as Reference Signal Signals required to perform the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Clock Signal CK Chip Select Signal CS Test Definition Notes from the Specification Test References See Table 103 LP...

Page 221: ...QSCK Delay is one cycle In example for tDQSCK Delay 1 tDQSCKm clock point is clock middle crosspoint that previous of closest Clock DQS For tDQSCK Delay 3 tDQSCKm clock point is clock middle crosspoint that three clock before with closest Clock DQS tDQSCK Delay is configurable in configuration page 9 Compare these tDQSCKm strobe point to tDQSCKm clock point as a tDQSCKm value Mathematically tDQSCK...

Page 222: ...ired Read Write separation Yes Signal s of Interest Data Strobe Signals supported by Data Signal Clock Signal CK as Reference Signal Optional signal s Chip Select Signal this signal is used to separate DQ signals from different rank of memory Signals required to perform the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Clock Signal CK Chip Select Signal CS Test Definition Notes fr...

Page 223: ...SCK Delay is one cycle In example for tDQSCK Delay 1 tDQSCKm clock point is clock middle crosspoint that previous of closest Clock DQS For tDQSCK Delay 3 tDQSCKm clock point is clock middle crosspoint that three clock before with closest Clock DQS tDQSCK Delay is configurable in configuration page 9 Compare these tDQSCKm strobe point to tDQSCKm clock point as a tDQSCKm value Mathematically tDQSCKm...

Page 224: ...14 Clock Timing CT Tests 208 DDR2 LP Compliance Testing Methods of Implementation ...

Page 225: ...amble Test Method of Implementation 234 tRPRE Read Preamble Test Method of Implementation 236 tRPST Read Postamble Test Method of Implementation 238 tHZ DQ Test Low Power DQ Out HIGH Impedance Time From Clock Test Method of Implementation 240 tHZ DQS Test Low Power DQS Out HIGH Impedance Time From Clock Test Method of Implementation 242 tLZ DQS Test Low Power DQS Low Impedance Time From Clock Test...

Page 226: ...e channels shown in Figure 30 are just examples For more information on the probe amplifiers and differential probe heads see Chapter 20 InfiniiMax Probing starting on page 351 Test Procedure 1 Start the automated test application as described in Starting the DDR2 LP Compliance Test Application on page 27 2 Ensure that the RAM reliability test software is running on the computer system where the D...

Page 227: ...at support LPDDR2 check the Low Power box 7 Type in or select the Device Identifier as well as User Description from the drop down list Enter your comments in the Comments text box 8 Click the Select Tests tab and check the tests you want to run Check the parent node or group to check all the available tests within the group 9 Follow the DDR2 LP Test application s task flow to set up the configura...

Page 228: ... the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Clock Signal CK Chip Select Signal CS optional Test Definition Notes from the Specification Test References See Table 41 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 and Table 42 Timing Parameters by Speed Grade DDR2 667 and DDR2 800 in the JEDEC Standard JESD79 2E Also see Table 41 Timing Parameters by Speed Grade DDR2 ...

Page 229: ...acquired signal 2 Take the first valid READ burst found 3 Find tHZEndPoint DQ of the said burst 4 Find the nearest rising Clock crossing 5 tHZ DQ is the time interval of the rising Clock edge s crossing point to the tHZEndPoint 6 Report tHZ DQ NOTE Some designs do not have tri state at VREF for example 0 9V This test is not guaranteed when this scenario happens as there is no significant point of ...

Page 230: ...ignal DQ Data Strobe Signal DQS Clock Signal CK Chip Select Signal CS optional Test Definition Notes from the Specification Test References See Table 41 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 and Table 42 Timing Parameters by Speed Grade DDR2 667 and DDR2 800 in the JEDEC Standard JESD79 2E Also see Table 41 Timing Parameters by Speed Grade DDR2 1066 in the JESD208 Table 128 Timing...

Page 231: ...he specification limit Measurement Algorithm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid READ burst found 3 Find tLZBeginPoint DQS of the said burst 4 Find the nearest Clock rising edge 5 tLZ DQS is the time interval of the rising Clock edge s crossing point to the tLZBeginPoint DQS 6 Report tLZ DQS ...

Page 232: ... Signal DQ Data Strobe Signal DQS Clock Signal CK Chip Select Signal CS optional Test Definition Notes from the Specification Test References See Table 41 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 and Table 42 Timing Parameters by Speed Grade DDR2 667 and DDR2 800 in the JEDEC Standard JESD79 2E Also see Table 41 Timing Parameters by Speed Grade DDR2 1066 in the JESD208 Table 130 Timi...

Page 233: ... the specification limit Measurement Algorithm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid READ burst found 3 Find tLZBeginPoint DQ of the said burst 4 Find the nearest Clock rising edge 5 tLZ DQ is the time interval of the rising Clock edge s crossing point to the tLZBeginPoint DQ 6 Report tLZ DQ ...

Page 234: ...perform the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Chip Select Signal CS optional Test Definition Notes from the Specification Table 132 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max DQS DQ skew for DQS and associated DQ signals tDQSQ x 350 x 300 ps 13 Parameter Symbol DDR...

Page 235: ... see Table 103 LPDDR2 AC Timing Table in the JESD209 2B PASS Condition The worst measured tDQSQ shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid READ burst found 3 Find all valid rising and falling DQ crossings at VREF in the said burst 4 For all DQ crossings found locate the nearest DQS crossing ri...

Page 236: ...orm the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Chip Select Signal CS optional Test Definition Notes from the Specification Table 135 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max DQ DQS output hold time from DQS tQH tHP tQHS x tHP tQHS x ps Parameter Symbol DDR2 667 DDR2 8...

Page 237: ...e JESD209 2B PASS Condition The worst measured tQH shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid READ burst found 3 Find all valid rising and falling DQ crossings at VREF in the said burst 4 For all DQ crossings found locate the nearest DQS rising falling crossing 5 Using the found DQS rising fal...

Page 238: ...ata Strobe Signal DQS Clock Signal CK Chip Select Signal CS optional Test Definition Notes from the Specification Test References See Table 41 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 and Table 42 Timing Parameters by Speed Grade DDR2 667 and DDR2 800 in the JEDEC Standard JESD79 2E Also see Table 41 Timing Parameters by Speed Grade DDR2 1066 in the JESD208 Table 138 Timing Parameter...

Page 239: ...nt Algorithm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid WRITE burst found 3 Find all valid rising DQS crossings in the said burst 4 For all DQS crossings found locate the nearest Clock rising crossing 5 Take the time difference from DQS crossing to Clock crossing as the tDQSS 6 Determine the worst result from the set of tDQSS measured ...

Page 240: ...he oscilloscope Data Signal DQ Data Strobe Signal DQS Chip Select Signal CS optional Test Definition Notes from the Specification Table 140 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max DQS input HIGH pulse width tDQSH 0 35 x 0 35 x tCK Parameter Symbol DDR2 667 DDR2 800 Units Specific Notes Min ...

Page 241: ...he JESD208 Also See Table 103 LPDDR2 AC Timing Table in the JESD209 2B PASS Condition The worst measured tDQSH shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid WRITE burst found 3 Find all valid rising and falling DQS crossings in the said burst 4 tDQSH is the time interval starting from a rising ed...

Page 242: ...the oscilloscope Data Signal DQ Data Strobe Signal DQS Chip Select Signal CS optional Test Definition Notes from the Specification Table 143 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max DQS input LOW pulse width tDQSL 0 35 x 0 35 x tCK Parameter Symbol DDR2 667 DDR2 800 Units Specific Notes Min ...

Page 243: ...he JESD208 Also See Table 103 LPDDR2 AC Timing Table in the JESD209 2B PASS Condition The worst measured tDQSL shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid WRITE burst found 3 Find all valid rising and falling DQS crossings in the said burst 4 tDQSL is the time interval starting from a falling e...

Page 244: ...rform the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Clock Signal CK Chip Select Signal CS optional Test Definition Notes from the Specification Table 146 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max DQS falling edge to CK setup time tDSS 0 2 x 0 2 x tCK avg Parameter Symbol ...

Page 245: ...e 103 LPDDR2 AC Timing Table in the JESD209 2B PASS Condition The worst measured tDSS shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid WRITE burst found 3 Find all valid falling DQS crossings in the said burst 4 For all falling DQS crossings found locate all nearest next rising Clock edges 5 tDSS is...

Page 246: ...orm the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Clock Signal CK Chip Select Signal CS optional Test Definition Notes from the Specification Table 149 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max DQS falling edge hold time from CK tDSH 0 2 x 0 2 x tCK Parameter Symbol DDR2 ...

Page 247: ...Table 103 LPDDR2 AC Timing Table in the JESD209 2B PASS Condition The worst measured tDSH shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid WRITE burst found 3 Find all valid falling DQS crossings in the said burst 4 For all falling DQS crossings found locate all nearest prior rising Clock edges 5 tD...

Page 248: ...different rank of memory Signals required to perform the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Chip Select Signal CS optional Test Definition Notes from the Specification Table 152 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max WRITE Postamble tWPST 0 4 0 6 0 4 0 6 tCK 10 ...

Page 249: ...Grade DDR2 1066 in the JESD208 Also See Table 103 LPDDR2 AC Timing Table in the JESD209 2B PASS Condition The measured tWPST shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid WRITE burst found 3 Find the tHZEndPoint DQS of the said burst 4 Find the last falling edge on DQS prior to the tHZEndPoint DQ...

Page 250: ...emory Signals required to perform the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Chip Select Signal CS optional Test Definition Notes from the Specification Table 155 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max WRITE Preamble tWPRE 0 35 x 0 35 x tCK Parameter Symbol DDR2 667...

Page 251: ...eed Grade DDR2 1066 in the JESD208 Also See Table 103 LPDDR2 AC Timing Table in the JESD209 2B PASS Condition The measured tWPRE shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid WRITE burst found 3 Find the tLZBeginPoint DQS of the said burst 4 Find the first rising edge on DQS of the found burst 5 ...

Page 252: ...ignals required to perform the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Chip Select Signal CS optional Test Definition Notes from the Specification Table 158 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max READ Preamble tRPRE 0 9 1 1 0 9 1 1 tCK 19 Parameter Symbol DDR2 667 DD...

Page 253: ...eed Grade DDR2 1066 in the JESD208 Also See Table 103 LPDDR2 AC Timing Table in the JESD209 2B PASS Condition The measured tRPRE shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid READ burst found 3 Find the tLZBeginPoint DQS of the said burst 4 Find the first rising edge on DQS of the found burst 5 t...

Page 254: ...k of memory Signals required to perform the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Chip Select Signal CS optional Test Definition Notes from the Specification Table 161 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max READ Postamble tRPST 0 4 0 6 0 4 0 6 tCK 19 Parameter Symb...

Page 255: ... Grade DDR2 1066 in the JESD208 Also See Table 103 LPDDR2 AC Timing Table in the JESD209 2B PASS Condition The measured tRPST shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid READ burst found 3 Find the tHZEndPoint DQS of the said burst 4 Find the last falling edge on DQS prior to the tHZEndPoint DQ...

Page 256: ...t READ Signal s of Interest Data Signal supported by Data Strobe Signal Clock Signal Optional signal s Chip Select Signal this signal is used to separate DQ signals from different rank of memory Signals required to perform the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Clock Signal CK Chip Select Signal CS optional Test Definition Notes from the Specification Test References Se...

Page 257: ...tDQSCK Clock point is the Clock middle crossing point that is prior to the closest Clock DQS If tDQSCK Delay 3 then the tDQSCK Clock point is the Clock middle crossing point three clock cycles before the closest Clock DQS tDQSCK Delay is configurable in the configuration page 5 Define BL bit length to be the number of DQS middle crossing points 6 Find RL BL 2 Clock edge Clock rising middle crossin...

Page 258: ...Data Strobe Signal supported by Data Signal Clock Signal CK as Reference Signal Optional signal s Chip Select Signal this signal is used to separate DQS signals from different rank of memory Signals required to perform the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Clock Signal CK Chip Select Signal CS optional Test Definition Notes from the Specification Test References See Ta...

Page 259: ... tDQSCK Delay cycle By default tDQSCK Delay is one cycle For example if tDQSCK Delay 1 then the tDQSCK Clock point is the Clock middle crossing point that is prior to the closest Clock DQS If tDQSCK Delay 3 then the tDQSCK Clock point is the Clock middle crossing point three clock cycles before the closest Clock DQS tDQSCK Delay is configurable in the configuration page 5 Define BL bit length to b...

Page 260: ...Data Strobe Signal supported by Data Signal Clock Signal CK as Reference Signal Optional signal s Chip Select Signal this signal is used to separate DQS signals from different rank of memory Signals required to perform the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Clock Signal CK Chip Select Signal CS optional Test Definition Notes from the Specification Test References See Ta...

Page 261: ...t immediately before the closest Clock DQS to tDQSCK Delay cycle By default tDQSCK Delay is one cycle For example if tDQSCK Delay 1 then the tDQSCK Clock point is the Clock middle crossing point that is prior to the closest Clock DQS If tDQSCK Delay 3 then the tDQSCK Clock point is the Clock middle crossing point three clock cycles before the closest Clock DQS tDQSCK Delay is configurable in the c...

Page 262: ...st Data Signal supported by Data Strobe Signal Clock Signal CK as Reference Signal Optional signal s Chip Select Signal this signal is used to separate DQ signals from different rank of memory Signals required to perform the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Clock Signal CK Chip Select Signal CS optional Test Definition Notes from the Specification Test References See ...

Page 263: ...erence which is the Clock middle crossing point immediately before the closest Clock DQS to tDQSCK Delay cycle By default tDQSCK Delay is one cycle For example if tDQSCK Delay 1 then the tDQSCK Clock point is the Clock middle crossing point that is prior to the closest Clock DQS If tDQSCK Delay 3 then the tDQSCK Clock point is the Clock middle crossing point three clock cycles before the closest C...

Page 264: ...Data Signal DQ Data Strobe Signal DQS Chip Select Signal CS optional Test Definition Notes from the Specification Test References See Table 103 LPDDR2 AC Timing Table in the JESD209 2B PASS Condition The worst measured tQSH shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid READ burst found 3 Find all...

Page 265: ...ata Signal DQ Data Strobe Signal DQS Chip Select Signal CS optional Test Definition Notes from the Specification Test References See Table 103 LPDDR2 AC Timing Table in the JESD209 2B PASS Condition The worst measured tQSL shall be within the specification limit Measurement Algorithm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid READ burst found 3 Find all ...

Page 266: ...erest Write Signal s of Interest Data Strobe Signal supported by Data Signal Clock Signal Optional signal s Chip Select Signal this signal is used to separate DQ signals from different rank of memory Signals required to perform the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Clock Signal CK Chip Select Signal CS optional Test Definition Notes from the Specification Test Referenc...

Page 267: ...oint first DQS rising edge as the tDQSS strobe point 5 Find the closest Clock DQS the Clock middle crossing point that is closest to the first DQS rising edge 6 Find the tDQSS Clock point which is the rising clock middle crossing point one cycle before the closest Clock DQS 7 Compare the tDQSS strobe point to the tDQSS clock point as the test result Mathematically the test result tDQSS strobe poin...

Page 268: ...ip Select Signal this signal is used to separate DQS signals from different rank of memory Signals required to perform the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Chip Select Signal CS optional Test Definition Notes from the Specification Test References See Table 78 Allowed Time Before Ringback tDVAC for CK_t CK_s and DQS_t DQS_c in the JESD209 2B PASS Condition The worst m...

Page 269: ...AC crossing point and ending at the following DQS falling VIHdiff AC crossing point 5 tDVAC Strobe is also the time interval starting from a DQS falling VILdiff AC crossing point and ending at the following DQS rising VILdiff AC crossing point 6 Collect all tDVAC Strobe results 7 Determine the worst result from the set of tDVAC Strobe measured 8 Report the worst result from the set of tDVAC Strobe...

Page 270: ...15 Data Strobe Timing DST Tests 254 DDR2 LP Compliance Testing Methods of Implementation ...

Page 271: ...d DQ and DM Input Setup Time with Derating Support Test Method of Implementation 283 tDH1 derate Single Ended DQ and DM Input Hold Time with Derating Support Test Method of Implementation 286 tVAC Data Time Above VIH AC Below VIL AC Test Method of Implementation 289 tDIPW DQ and DM Input Pulse Width Test Method of Implementation 291 tQHP Data Half Period Test Method of Implementation 292 tDS DQ an...

Page 272: ... number of probe connections Typically you need minimum three probe connections to run the tests You can use any of the oscilloscope channels as Pin Under Test PUT source channel You can identify the channels used for each signal in the Configuration tab of the DDR2 LP Compliance Test Application The channels shown in Figure 32 are just examples For more information on the probe amplifiers and dif...

Page 273: ...o the PUTs on the DDR2 LPDDR2 devices 4 Connect the oscilloscope probes to any channels of the oscilloscope 5 In the DDR2 LP Test application click the Set Up tab 6 Select the Speed Grade options For Data Timing Tests you can select any speed grade within the selection DDR2 400 DDR2 533 DDR2 667 DDR2 800 DDR2 1066 To select a LPDDR2 Speed Grade option for tests that support LPDDR2 check the Low Po...

Page 274: ...6 Data Timing Tests 258 DDR2 LP Compliance Testing Methods of Implementation 9 Follow the DDR2 LP Test application s task flow to set up the configuration options run the tests and view the tests results ...

Page 275: ... on the oscilloscope Data Signal DQ or Data Mask Signal DM Data Strobe Signal DQS this must use a differential DQS connection Chip Select Signal CS optional Test Definition Notes from the Specification Table 172 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max DQ and DM input setup time differential...

Page 276: ...is defined as the time between the DQ crossing and the DQS crossing 7 Collect all tDS 8 Find the worst tDS among the measured values and report the value as the test result 9 Measure the nominal slew rate on the DQ and DQS edges where the worst tDS was found For DQ Falling Slew Rate VREF VIL AC tF For DQ Rising Slew Rate VIH AC VREF tR tF and tR are the transition time respectively For DQS Rising ...

Page 277: ...n the oscilloscope Data Signal DQ or Data Mask Signal DM Data Strobe Signal DQS this must use a differential DQS connection Chip Select Signal CS optional Test Definition Notes from the Specification Table 175 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max DQ and DM input hold time differential st...

Page 278: ...H is defined as the time between the DQ crossing and the DQS crossing 7 Collect all tDH 8 Find the worst tDH among the measured values and report the value as the test result 9 Measure the nominal slew rate on the DQ and DQS edges where the worst tDH was found For DQ Falling Slew Rate VREF VIL DC tF For DQ Rising Slew Rate VIH DC VREF tR tF and tR are the transition time respectively For DQS Risin...

Page 279: ...ignal DQ or Data Mask Signal DM Data Strobe Signal DQS this must use a differential DQS connection Chip Select Signal CS optional Test Definition Notes from the Specification Table 178 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max DQ and DM input setup time differential strobe tDS base 150 x 100 ...

Page 280: ...5 128 103 116 Table 180 DDR2 667 800 tDS tDH derating with differential data strobe tDS tDH derating values for DDR2 667 DDR2 800 All units in ps the note applies to the entire table DQS DQS Differential Slew Rate 4 0 V ns 3 0 V ns 2 0 V ns 1 8 V ns tDS tDH tDS tDH tDS tDH tDS tDH DQ Slew Rate V ns 2 0 100 45 100 45 100 45 1 5 67 21 67 21 67 21 79 33 1 0 0 0 0 0 0 0 12 12 0 9 5 14 5 14 7 2 0 8 13 ...

Page 281: ...1066 Parameter Symbol DDR2 1066 Units Specific Notes Min Max DQ and DM input setup time tDS base 0 x ps 6 7 8 17 23 26 Table 182 DDR2 1066 tDS tDH derating with differential data strobe tDS tDH derating values for DDR2 1066 All units in ps the note applies to the entire table DQS DQS Differential Slew Rate 4 0 V ns 3 0 V ns 2 0 V ns 1 8 V ns tDS tDH tDS tDH tDS tDH tDS tDH DQ Slew Rate V ns 2 0 10...

Page 282: ...5 128 103 116 Table 180 DDR2 667 800 tDS tDH derating with differential data strobe tDS tDH derating values for DDR2 667 DDR2 800 All units in ps the note applies to the entire table DQS DQS Differential Slew Rate 4 0 V ns 3 0 V ns 2 0 V ns 1 8 V ns tDS tDH tDS tDH tDS tDH tDS tDH DQ Slew Rate V ns 2 0 100 45 100 45 100 45 1 5 67 21 67 21 67 21 79 33 1 0 0 0 0 0 0 0 12 12 0 9 5 14 5 14 7 2 0 8 13 ...

Page 283: ...1066 Parameter Symbol DDR2 1066 Units Specific Notes Min Max DQ and DM input setup time tDS base 0 x ps 6 7 8 17 23 26 Table 182 DDR2 1066 tDS tDH derating with differential data strobe tDS tDH derating values for DDR2 1066 All units in ps the note applies to the entire table DQS DQS Differential Slew Rate 4 0 V ns 3 0 V ns 2 0 V ns 1 8 V ns tDS tDH tDS tDH tDS tDH tDS tDH DQ Slew Rate V ns 2 0 10...

Page 284: ... 7 2 30 14 18 26 6 38 6 0 6 10 59 2 47 14 35 26 23 38 11 0 5 24 89 12 77 0 65 12 53 0 4 52 140 40 128 28 116 Table 183 Data Setup and Hold Base Values Symbol LPDDR2 Units Reference 1066 933 800 667 533 466 tDS base 10 15 50 130 210 230 ps VIH L AC VREF AC 220mV Symbol LPDDR2 Units Reference 400 333 266 200 tDS base 180 300 450 700 ps VIH L AC VREF AC 300mV Table 182 DDR2 1066 tDS tDH derating with...

Page 285: ...tDS tDH tDS tDH DQ Slew Rate V ns 2 0 110 65 110 65 110 65 1 5 74 43 73 43 73 43 89 59 1 0 0 0 0 0 0 0 16 16 0 9 3 5 3 5 13 11 0 8 8 13 8 3 0 7 2 6 0 6 0 5 0 4 tDS tDH derating in ps AC DC based AC220 Threshold VIH AC VREF DC 220mV VIL AC VREF DC 220mV DC130 Threshold VIH DC VREF DC 130mV VIL DC VREF DC 130mV DQS_t DQS_c Differential Slew Rate 1 6 V ns 1 4 V ns 1 2 V ns 1 0 V ns tDS tDH tDS tDH tD...

Page 286: ...F DC 300mV VIL AC VREF DC 300mV DC200 Threshold VIH DC VREF DC 200mV VIL DC VREF DC 200mV DQS_t DQS_c Differential Slew Rate 4 0 V ns 3 0 V ns 2 0 V ns 1 8 V ns tDS tDH tDS tDH tDS tDH tDS tDH DQ Slew Rate V ns 2 0 150 100 150 100 150 100 1 5 100 67 100 67 100 67 116 83 1 0 0 0 0 0 0 0 16 16 0 9 4 8 4 8 12 8 0 8 12 20 4 4 0 7 3 18 0 6 0 5 0 4 tDS tDH derating in ps AC DC based AC300 Threshold VIH ...

Page 287: ...hm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid WRITE burst found 3 Find all valid rising DQ crossings that cross VIH AC in the burst 4 Find all valid falling DQ crossings that cross VIL DC in the same burst 5 For all DQ crossings found locate all next DQS crossings that cross 0V 6 tDS is defined as the time between the DQ crossing and the DQS crossing 7 C...

Page 288: ...gnal DQ or Data Mask Signal DM Data Strobe Signal DQS this must use a differential DQS connection Chip Select Signal CS optional Test Definition Notes from the Specification Table 186 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max DQ and DM input hold time differential strobe tDH base 275 x 225 x ...

Page 289: ...5 128 103 116 Table 188 DDR2 667 800 tDS tDH derating with differential data strobe tDS tDH derating values for DDR2 667 DDR2 800 All units in ps the note applies to the entire table DQS DQS Differential Slew Rate 4 0 V ns 3 0 V ns 2 0 V ns 1 8 V ns tDS tDH tDS tDH tDS tDH tDS tDH DQ Slew Rate V ns 2 0 100 45 100 45 100 45 1 5 67 21 67 21 67 21 79 33 1 0 0 0 0 0 0 0 12 12 0 9 5 14 5 14 7 2 0 8 13 ...

Page 290: ...1066 Parameter Symbol DDR2 1066 Units Specific Notes Min Max DQ and DM input hold time tDH base 75 x ps 6 7 8 18 23 26 Table 190 DDR2 1066 tDS tDH derating with differential data strobe tDS tDH derating values for DDR2 1066 All units in ps the note applies to the entire table DQS DQS Differential Slew Rate 4 0 V ns 3 0 V ns 2 0 V ns 1 8 V ns tDS tDH tDS tDH tDS tDH tDS tDH DQ Slew Rate V ns 2 0 10...

Page 291: ...7 2 30 14 18 26 6 38 6 0 6 10 59 2 47 14 35 26 23 38 11 0 5 24 89 12 77 0 65 12 53 0 4 52 140 40 128 28 116 Table 191 Data Setup and Hold Base Values Symbol LPDDR2 Units Reference 1066 933 800 667 533 466 tDH base 80 105 140 220 300 320 ps VIH L DC VREF DC 130mV Symbol LPDDR2 Units Reference 400 333 266 200 tDH base 280 400 550 800 ps VIH L DC VREF DC 200mV Table 190 DDR2 1066 tDS tDH derating wit...

Page 292: ...tDS tDH tDS tDH DQ Slew Rate V ns 2 0 110 65 110 65 110 65 1 5 74 43 73 43 73 43 89 59 1 0 0 0 0 0 0 0 16 16 0 9 3 5 3 5 13 11 0 8 8 13 8 3 0 7 2 6 0 6 0 5 0 4 tDS tDH derating in ps AC DC based AC220 Threshold VIH AC VREF DC 220mV VIL AC VREF DC 220mV DC130 Threshold VIH DC VREF DC 130mV VIL DC VREF DC 130mV DQS_t DQS_c Differential Slew Rate 1 6 V ns 1 4 V ns 1 2 V ns 1 0 V ns tDS tDH tDS tDH tD...

Page 293: ...F DC 300mV VIL AC VREF DC 300mV DC200 Threshold VIH DC VREF DC 200mV VIL DC VREF DC 200mV DQS_t DQS_c Differential Slew Rate 4 0 V ns 3 0 V ns 2 0 V ns 1 8 V ns tDS tDH tDS tDH tDS tDH tDS tDH DQ Slew Rate V ns 2 0 150 100 150 100 150 100 1 5 100 67 100 67 100 67 116 83 1 0 0 0 0 0 0 0 16 16 0 9 4 8 4 8 12 8 0 8 12 20 4 4 0 7 3 18 0 6 0 5 0 4 tDS tDH derating in ps AC DC based AC300 Threshold VIH ...

Page 294: ...hm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid WRITE burst found 3 Find all valid rising DQ crossings that cross VIl DC in the burst 4 Find all valid falling DQ crossings that cross VIH DC in the same burst 5 For all DQ crossings found locate all next DQS crossings that cross 0V 6 tDH is defined as the time between the DQ crossing and the DQS crossing 7 C...

Page 295: ... signal s Chip Select Signal this signal is used to separate DQ signals from different rank of memory Signals required to perform the test on the oscilloscope Data Signal DQ or Data Mask Signal DM Data Strobe Signal DQS this must use a single ended DQS connection Chip Select Signal CS optional Test Definition Notes from the Specification Test References See Table 41 Timing Parameters by Speed Grad...

Page 296: ...QS crossing 7 Collect all tDS1 8 Find the worst tDS1 among the measured values and report the value as the test result 9 Measure the nominal slew rate on the DQ and DQS edges where worst tDS1 was found 10 For DQ DQS Falling Slew Rate VREF VIL AC tF For DQ Rising Slew Rate VIH AC VREF tR tF and tR are the transition time respectively 11 Report the nominal slew rate for DQ and DQS 12 Measure the tan...

Page 297: ... signal s Chip Select Signal this signal is used to separate DQ signals from different rank of memory Signals required to perform the test on the oscilloscope Data Signal DQ or Data Mask Signal DM Data Strobe Signal DQS this must use a single ended DQS connection Chip Select Signal CS optional Test Definition Notes from the Specification Test References See Table 41 Timing Parameters by Speed Grad...

Page 298: ...the measured values and report the value as the test result 9 Measure the nominal slew rate on the DQ and DQS edges where worst tDH1 was found For DQ Falling Slew Rate VREF VIL AC tF For DQ Rising Slew Rate VIH AC VREF tR tF and tR are the transition time respectively For DQS Rising Slew Rate VHITHRES 0V tR For DQS Falling Slew Rate 0V VLOTHRES tF tF and tR are the transition time respectively 10 ...

Page 299: ...nals required to perform the test on the oscilloscope Data Signal DQ or Data Mask Signal DM Data Strobe Signal DQS this must use a differential DQS connection Chip Select Signal CS optional Test Definition Notes from the Specification Table 196 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max DQ and DM input setup time s...

Page 300: ...The worst measured tDS1 shall be within the specification limit tDS1 tDH1 derating values for DDR2 400 DDR2 533 All units in ps the note applies to the entire table DQS Single Ended Slew Rate 0 8 V ns 0 7 V ns 0 6 V ns 0 5 V ns 0 4 V ns tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH DQ Slew Rate V ns 2 0 1 5 1 0 7 13 0 9 18 27 29 45 0 8 32 44 43 62 60 86 0 7 50 67 61 85 78 109 108 152 0 6 74 96 85 114 10...

Page 301: ...e burst 5 For all DQ crossings found locate all prior DQS falling crossings that cross VIH DC and all prior DQS rising crossings that cross VIL DC 6 tDS1 is defined as the time between the DQ crossing and the DQS crossing 7 Collect all tDS1 8 Find the worst tDS1 among the measured values and report the value as the test result 9 Measure the mean slew rate for all the DQ and DQS edges 10 Use the me...

Page 302: ...als required to perform the test on the oscilloscope Data Signal DQ or Data Mask Signal DM Data Strobe Signal DQS this must use a differential DQS connection Chip Select Signal CS optional Test Definition Notes from the Specification Table 198 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max DQ and DM input hold time sin...

Page 303: ...The worst measured tDH1 shall be within the specification limit tDS1 tDH1 derating values for DDR2 400 DDR2 533 All units in ps the note applies to the entire table DQS Single Ended Slew Rate 0 8 V ns 0 7 V ns 0 6 V ns 0 5 V ns 0 4 V ns tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH DQ Slew Rate V ns 2 0 1 5 1 0 7 13 0 9 18 27 29 45 0 8 32 44 43 62 60 86 0 7 50 67 61 85 78 109 108 152 0 6 74 96 85 114 10...

Page 304: ...e burst 5 For all DQ crossings found locate all prior DQS rising crossings that cross VIH AC and all prior DQS falling crossings that cross VIL AC 6 tDH1 is defined as the time between the DQ crossing and the DQS crossing 7 Collect all tDH1 8 Find the worst tDH1 among the measured values and report the value as the test result 9 Measure the mean slew rate for all the DQ and DQS edges 10 Use the me...

Page 305: ...ct Signal this signal is used to separate DQS signals from different rank of memory Signals required to perform the test on the oscilloscope Data Signal DQ Data Strobe Signal DQS Chip Select Signal CS optional Test Definition Notes from the Specification Test References See Table 111 Required time tVAC above VIH AC below VIL AC for valid transition in the JESD209 2B PASS Condition The worst measur...

Page 306: ...IH AC crossing point and ending at the following DQ falling VIH AC crossing point 5 tVAC Data is also the time interval starting from a DQ falling VIL AC crossing point and ending at the following DQ rising VIL AC crossing point 6 Collect all tVAC Data results 7 Determine the worst result from the set of tVAC Data measured 8 Report the worst result from the set of tVAC Data measured No compliance ...

Page 307: ...al CS optional Test Definition Notes from the Specification Test References See Table 103 LPDDR2 AC Timing Table in the JEDEC Standard JESD209 2B PASS Condition The worst measured tDIPW should be within the specification limit Measurement Algorithm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid WRITE burst found 3 Find all of the valid rising and falling DQ ...

Page 308: ...CS optional Test Definition Notes from the Specification Test References See Table 103 LPDDR2 AC Timing Table in the JEDEC Standard JESD209 2B PASS Condition The worst measured tQHP should be within the specification limit Measurement Algorithm 1 Acquire and split read and write burst of the acquired signal 2 Take the first valid WRITE burst found 3 Find all of the valid rising and falling DQ cros...

Page 309: ... Signal supported by Data Strobe Signal Optional signal s Chip Select Signal this signal is used to separate DQ signals from different rank of memory Signals required to perform the test on the oscilloscope Data Signal DQ or Data Mask Signal DM Data Strobe Signal DQS This must use a differential DQS connection Chip Select Signal CS optional Test Definition Notes from the Specification Test Referen...

Page 310: ... all tDS 8 Find the worst tDS among the measured value and report the value as the test result 9 Measure nominal slew rate on the DQ and DQS edges where worst tDS is found For DQ Falling Slew Rate VREF VIL AC tF For DQ Rising Slew Rate VIH AC VREF tR tF and tR are the transition time respectively For DQS Rising Slew Rate VHITHRES 0V tR For DQS Falling Slew Rate 0V VLOTHRES tF tF and tR are the tra...

Page 311: ... Signal supported by Data Strobe Signal Optional signal s Chip Select Signal this signal is used to separate DQ signals from different rank of memory Signals required to perform the test on the oscilloscope Data Signal DQ or Data Mask Signal DM Data Strobe Signal DQS This must use a differential DQS connection Chip Select Signal CS optional Test Definition Notes from the Specification Test Referen...

Page 312: ...all tDH 8 Find the worst tDH among the measured value and report the value as the test result 9 Measure nominal slew rate on the DQ and DQS edges where worst tDH is found For DQ Falling Slew Rate VREF VIL DC tF For DQ Rising Slew Rate VIH DC VREF tR tF and tR are the transition time respectively For DQS Rising Slew Rate VHITHRES 0V tR For DQS Falling Slew Rate 0V VLOTHRES tF tF and tR are the tran...

Page 313: ...VIH AC Below VIL AC Test Method of Implementation 318 tIPW Address and Control Input Pulse Width Test Method of Implementation 320 tISCKE CKE Input Setup Time Test Method of Implementation 322 tIHCKE CKE Input Hold Time Test Method of Implementation 323 tISCKEb CKE Input Setup Time Boot Parameter Test Method of Implementation 324 tIHCKEb CKE Input Hold Time Boot Parameter Test Method of Implementa...

Page 314: ...on The channels shown in Figure 34 are just examples For more information on the probe amplifiers and differential probe heads see Chapter 20 InfiniiMax Probing starting on page 351 Test Procedure 1 Start the automated test application as described in Starting the DDR2 LP Compliance Test Application on page 27 2 Ensure that the RAM reliability test software is running on the computer system where ...

Page 315: ...ts that support LPDDR2 check the Low Power box 7 Type in or select the Device Identifier as well as User Description from the drop down list Enter your comments in the Comments text box 8 Click the Select Tests tab and check the tests you want to run Check the parent node or group to check all the available tests within the group 9 Follow the DDR2 LP Test application s task flow to set up the conf...

Page 316: ...and Address Clock Signal Test Definition Notes from the Specification Table 205 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max Address and control input setup time tIS base 350 x 250 x ps 5 7 9 22 Parameter Symbol DDR2 667 DDR2 800 Units Specific Notes Min Max Min Max Address and control input set...

Page 317: ... the respective clock crossing point should be within the specification limit Measurement Algorithm 1 Pre condition the oscilloscope settings 2 Trigger on both edges rising or falling of the address control signal under test 3 Find all of the crossings on the rising edge of the signal under test that cross VIH AC 4 Find all of the crossing on the falling edge of the signal under test that cross VI...

Page 318: ...nd Address Clock Signal Test Definition Notes from the Specification Table 208 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max Address and control input hold time tIH base 475 x 375 x ps 5 7 9 23 Parameter Symbol DDR2 667 DDR2 800 Units Specific Notes Min Max Min Max Address and control input hold ...

Page 319: ...Measurement Algorithm 1 Pre condition the oscilloscope settings 2 Trigger on both edges rising or falling of the address control signal under test 3 Find all of the crossings on the rising edge of the signal under test that cross VIL DC 4 Find all of the crossing on the falling edge of the signal under test that cross VIH DC 5 For all crossings locate the nearest Clock crossing that crosses 0V Not...

Page 320: ...upported DDR2 LPDDR2 Signal cycle of interest WRITE Signal s of Interest Address Signal OR Control Signal OR Command Address Clock Signal Signals required to perform the test on the oscilloscope Address Signal OR Control Signal OR Command Address Clock Signal Test Definition Notes from the Specification Table 211 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Paramete...

Page 321: ...d Address Slew Rate V ns 4 0 187 94 217 124 247 154 ps 1 3 5 179 89 200 119 239 149 3 0 167 83 197 113 227 143 2 5 150 75 180 105 210 135 2 0 125 45 155 75 185 105 1 5 83 21 113 51 143 81 1 0 0 0 30 30 60 60 0 9 11 14 19 16 49 46 0 8 25 31 5 1 35 29 0 7 43 54 13 24 17 6 0 6 67 83 37 53 7 23 0 5 110 125 80 95 50 65 0 4 175 188 145 158 115 128 0 3 285 292 255 262 225 232 0 25 350 375 320 345 290 315...

Page 322: ...3 0 133 83 163 113 193 143 2 5 120 75 150 105 180 135 2 0 100 45 130 75 160 105 1 5 67 21 97 51 127 81 1 0 0 0 30 30 60 60 0 9 5 14 25 16 55 46 0 8 13 31 17 1 47 29 0 7 22 54 8 24 38 6 0 6 34 83 4 53 26 23 0 5 60 125 30 95 0 65 0 4 100 188 70 158 40 128 0 3 168 292 138 262 108 232 0 25 200 375 170 345 140 315 0 2 325 500 295 470 265 440 0 15 517 708 487 678 457 648 0 1 1000 1125 970 1095 940 1065 ...

Page 323: ... 2 0 100 45 130 75 160 105 1 5 67 21 97 51 127 81 1 0 0 0 30 30 60 60 0 9 5 14 25 16 55 46 0 8 13 31 17 1 47 29 0 7 22 54 8 24 38 6 0 6 34 83 4 53 26 23 0 5 60 125 30 95 0 65 0 4 100 188 70 158 40 128 0 3 168 292 138 262 108 232 0 25 200 375 170 345 140 315 0 2 325 500 295 470 265 440 0 15 517 708 487 678 457 648 0 1 1000 1125 970 1095 940 1065 Table 216 CA and CS_n Setup and Hold Base Values for ...

Page 324: ... tIH tIS tIH tIS tIH CA CS_n Slew Rate V ns 2 0 110 65 110 65 110 65 1 5 74 43 73 43 73 43 89 59 1 0 0 0 0 0 0 0 16 16 0 9 3 5 3 5 13 11 0 8 8 13 8 3 0 7 2 6 0 6 0 5 0 4 tIS tIH derating in ps AC DC based AC220 Threshold VIH AC VREF DC 220mV VIL AC VREF DC 220mV DC130 Threshold VIH DC VREF DC 130mV VIL DC VREF DC 130mV CK_t CK_c Differential Slew Rate 1 6 V ns 1 4 V ns 1 2 V ns 1 0 V ns tIS tIH tI...

Page 325: ... AC VREF DC 300mV DC200 Threshold VIH DC VREF DC 200mV VIL DC VREF DC 200mV DQS_t DQS_c Differential Slew Rate 4 0 V ns 3 0 V ns 2 0 V ns 1 8 V ns tIS tIH tIS tIH tIS tIH tIS tIH CA CS_n Slew Rate V ns 2 0 150 100 150 100 150 100 1 5 100 67 100 67 100 67 116 83 1 0 0 0 0 0 0 0 16 16 0 9 4 8 4 8 12 8 0 8 12 20 4 4 0 7 3 18 0 6 0 5 0 4 tDS tDH derating in ps AC DC based AC300 Threshold VIH AC VREF D...

Page 326: ...her rising or falling edge of the address control signal under test 3 Find all crossings on rising edge of the signal under test that cross VIH AC 4 Find all crossings on falling edge of the signal under test that cross VIL AC 5 For all the crossings found locate the nearest Clock crossings that cross 0V Note For LPDDR2 with PUT CA option the Clock crossing could be Clock rising or Clock falling F...

Page 327: ...upported DDR2 LPDDR2 Signal cycle of interest WRITE Signal s of Interest Address Signal OR Control Signal OR Command Address Clock Signal Signals required to perform the test on the oscilloscope Address Signal OR Control Signal OR Command Address Clock Signal Test Definition Notes from the Specification Table 219 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Paramete...

Page 328: ...d Address Slew Rate V ns 4 0 187 94 217 124 247 154 ps 1 3 5 179 89 200 119 239 149 3 0 167 83 197 113 227 143 2 5 150 75 180 105 210 135 2 0 125 45 155 75 185 105 1 5 83 21 113 51 143 81 1 0 0 0 30 30 60 60 0 9 11 14 19 16 49 46 0 8 25 31 5 1 35 29 0 7 43 54 13 24 17 6 0 6 67 83 37 53 7 23 0 5 110 125 80 95 50 65 0 4 175 188 145 158 115 128 0 3 285 292 255 262 225 232 0 25 350 375 320 345 290 315...

Page 329: ...3 0 133 83 163 113 193 143 2 5 120 75 150 105 180 135 2 0 100 45 130 75 160 105 1 5 67 21 97 51 127 81 1 0 0 0 30 30 60 60 0 9 5 14 25 16 55 46 0 8 13 31 17 1 47 29 0 7 22 54 8 24 38 6 0 6 34 83 4 53 26 23 0 5 60 125 30 95 0 65 0 4 100 188 70 158 40 128 0 3 168 292 138 262 108 232 0 25 200 375 170 345 140 315 0 2 325 500 295 470 265 440 0 15 517 708 487 678 457 648 0 1 1000 1125 970 1095 940 1065 ...

Page 330: ... 0 100 45 130 75 160 105 1 5 67 21 97 51 127 81 1 0 0 0 30 30 60 60 0 9 5 14 25 16 55 46 0 8 13 31 17 1 47 29 0 7 22 54 8 24 38 6 0 6 34 83 4 53 26 23 0 5 60 125 30 95 0 65 0 4 100 188 70 158 40 128 0 3 168 292 138 262 108 232 0 25 200 375 170 345 140 315 0 2 325 500 295 470 265 440 0 15 517 708 487 678 457 648 0 1 1000 1125 970 1095 940 1065 Table 224 CA and CS_n Setup and Hold Base Values for 1V...

Page 331: ... tIH tIS tIH tIS tIH CA CS_n Slew Rate V ns 2 0 110 65 110 65 110 65 1 5 74 43 73 43 73 43 89 59 1 0 0 0 0 0 0 0 16 16 0 9 3 5 3 5 13 11 0 8 8 13 8 3 0 7 2 6 0 6 0 5 0 4 tIS tIH derating in ps AC DC based AC220 Threshold VIH AC VREF DC 220mV VIL AC VREF DC 220mV DC130 Threshold VIH DC VREF DC 130mV VIL DC VREF DC 130mV CK_t CK_c Differential Slew Rate 1 6 V ns 1 4 V ns 1 2 V ns 1 0 V ns tIS tIH tI...

Page 332: ...IL AC VREF DC 300mV DC200 Threshold VIH DC VREF DC 200mV VIL DC VREF DC 200mV CK_t CK_c Differential Slew Rate 4 0 V ns 3 0 V ns 2 0 V ns 1 8 V ns tIS tIH tIS tIH tIS tIH tIS tIH CA CS_n Slew Rate V ns 2 0 150 100 150 100 150 100 1 5 100 67 100 67 100 67 116 83 1 0 0 0 0 0 0 0 16 16 0 9 4 8 4 8 12 8 0 8 12 20 4 4 0 7 3 18 0 6 0 5 0 4 tDS tDH derating in ps AC DC based AC300 Threshold VIH AC VREF D...

Page 333: ...er rising or falling edge of the address control signal under test 3 Find all crossings on rising edge of the signal under test that cross VIL DC 4 Find all crossings on falling edge of the signal under test that cross VIH DC 5 For all the crossings found locate the nearest Clock crossings that cross 0V Note For LPDDR2 with PUT CA option the Clock crossing could be Clock rising or Clock falling Fo...

Page 334: ... No Signal s of Interest Command Address Signal LPDDR2 only OR Control Signal Signals required to perform the test on the oscilloscope Command Address Signal OR Control Signal Test Definition Notes from the Specification Test References See Table 107 Required time tVAC above VIH AC below VIL AC for valid transition in the JESD209 2B PASS Condition The worst measured tVAC CS CA should be within the...

Page 335: ... AC 5 tVAC CS CA is the time interval starting from a rising VIH AC crossing point and ending at the following falling VIH AC crossing point 6 tVAC CS CA is also the time interval starting from a falling VIL AC crossing point and ending at the following rising VIL AC crossing point 7 Collect all tVAC CS CA results 8 Determine the worst result from the set of tVAC CS CA measured 9 Report the worst ...

Page 336: ...ommand Address Signal LPDDR2 only OR Control Signal Test Definition Notes from the Specification Table 228 Timing Parameters by Speed Grade DDR2 400 and DDR2 533 DDR2 667 and DDR2 800 Parameter Symbol DDR2 400 DDR2 533 Units Specific Notes Min Max Min Max Control Address input pulse width for each input tIPW 0 6 x 0 6 x tCK Parameter Symbol DDR2 667 DDR2 800 Units34 Specific Notes Min Max Min Max ...

Page 337: ...in the JEDEC Standard JESD209 2B PASS Condition The worst measured tIPW shall be within the specification limit Measurement Algorithm 1 Pre condition the oscilloscope settings 2 Triggered on either rising or falling edge of the command address control signal under test 3 Find all crossings on rising falling edge of the signal under test that cross VREF 4 tIPW is time started from a rising falling ...

Page 338: ...ion The measured time interval between Clock Enable CKE setup time to respective clock crossing point shall be within the specification limit Measurement Algorithm 1 Pre condition the oscilloscope 2 Triggered on either rising or falling edge of the Clock Enable signal under test 3 Find all crossings on rising edge of the signal under test that cross VIH AC 4 Find all crossings on falling edge of t...

Page 339: ...ion The measured time interval between Clock Enable CKE hold time to respective clock crossing point shall be within the specification limit Measurement Algorithm 1 Pre condition the oscilloscope 2 Triggered on either rising or falling edge of the Clock Enable signal under test 3 Find all crossings on rising edge of the signal under test that cross VIL DC 4 Find all crossings on falling edge of th...

Page 340: ... PASS Condition The measured time interval between Clock Enable CKE setup time to respective clock crossing point shall be within the specification limit Measurement Algorithm 1 Pre condition the oscilloscope 2 Triggered on either rising or falling edge of the Clock Enable signal under test 3 Find all crossings on rising edge of the signal under test that cross VIH AC 4 Find all crossings on falli...

Page 341: ... PASS Condition The measured time interval between Clock Enable CKE hold time to respective clock crossing point shall be within the specification limit Measurement Algorithm 1 Pre condition the oscilloscope 2 Triggered on either rising or falling edge of the Clock Enable signal under test 3 Find all crossings on rising edge of the signal under test that cross VIL DC 4 Find all crossings on fallin...

Page 342: ...17 Command and Address Timing CAT Tests 326 DDR2 LP Compliance Testing Methods of Implementation ...

Page 343: ...est for Read Cycle Method of Implementation 331 User Defined Real Time Eye Diagram Test for Write Cycle Method of Implementation 332 This section provides the Methods of Implementation MOIs for Advanced Debug Mode Read Write Eye Diagram tests using a Keysight 80000B or 90000A Series Infiniium oscilloscope recommended InfiniiMax 116xA or 113xA probe amplifiers differential solder in probe head and ...

Page 344: ...niiMax Probing starting on page 351 Test Procedure 1 Start the automated test application as described in Starting the DDR2 LP Compliance Test Application on page 27 2 Ensure that the RAM reliability test software is running on the computer systems where the DDR2 Device Under Test DUT is attached This software will perform a test on all the unused RAM on the system by producing repetitive bursts o...

Page 345: ...d Write Eye Diagram Tests 18 7 Click this button to view or select test mask files for eye diagram tests 8 Advanced Debug Mode also allows you to type in the data rate of the DUT signal Figure 37 Selecting Custom Test Mode Figure 38 Selecting Test Mask for Eye Diagram Tests ...

Page 346: ...down list Enter your comments in the Comments text box 10 Click the Select Tests tab and check the tests you want to run Check the parent node or group to check all the available tests within the group 11 Follow the DDR2 Test application s task flow to set up the configuration options run the tests and view the tests results Figure 39 Selecting Advanced Debug Read Write Eye Diagram Tests ...

Page 347: ...in order to generate an eye diagram for the DDR2 data READ cycle This additional feature of mask test allows you to perform evaluation and debugging on the created eye diagram The test will show a fail status if the total failed waveforms is greater than 0 Signals of Interest Signal cycle of interest READ Signal s of Interest Data Signal supported by Data Strobe Signal Signals required to perform ...

Page 348: ...ye diagram for the DDR2 data WRITE cycle This additional feature of mask test allows you to perform evaluation and debugging on the created eye diagram The test will show a fail status if the total failed waveforms is greater than 0 Signals of Interest Signal cycle of interest WRITE Signal s of Interest Data Signal supported by Data Strobe Signal Signals required to perform the test on the oscillo...

Page 349: ... the Infiniium Oscilloscope and Probe Required Equipment for Oscilloscope Calibration 334 Internal Calibration 335 Required Equipment for Probe Calibration 338 Probe Calibration 339 Verifying the Probe Calibration 347 This section describes the Keysight Infiniium digital storage oscilloscope calibration procedures ...

Page 350: ...wing equipment Keyboard qty 1 provided with the Keysight Infiniium oscilloscope Mouse qty 1 provided with the Keysight Infiniium oscilloscope Precision 3 5 mm BNC to SMA male adapter Keysight p n 54855 67604 qty 2 provided with the Keysight Infiniium oscilloscope Calibration cable provided with the 80000B and 90000A series Infiniium oscilloscopes Use a good quality 50 BNC cable BNC shorting cap Fi...

Page 351: ...sing the power button located on the lower left of the front panel d Allow the oscilloscope to warm up at least 30 minutes prior to starting the calibration procedure in step 3 below 2 Locate and prepare the accessories that will be required for the internal calibration a Locate the BNC shorting cap b Locate the calibration cable c Locate the two Keysight precision SMA BNC adapters d Attach one SM...

Page 352: ...P Compliance Testing Methods of Implementation 4 Referring to Figure 42 below perform the following steps to start the calibration b Uncheck the Cal Memory Protect checkbox c Click the Start button to begin the calibration Figure 42 Oscilloscope Calibration Window ...

Page 353: ...e prompted with a Calibration Complete message window Click the OK button to close this window g Confirm that the Vertical and Trigger Calibration Status for all Channels passed h Click the Close button to close the calibration window i The internal calibration is completed j Read NOTE below NOTE These steps do not need to be performed every time a test is run However if the ambient temperature ch...

Page 354: ...ld calibrate the probes Calibration of the solder in probe heads consist of a vertical calibration and a skew calibration The vertical calibration should be performed before the skew calibration Both calibrations should be performed for best probe measurement performance The calibration procedure requires the following parts BNC male to SMA male adaptor Deskew fixture 50 SMA terminator ...

Page 355: ...C of the Infiniium oscilloscope 4 Connect the probe to an oscilloscope channel 5 To minimize the wear and tear on the probe head it should be placed on a support to relieve the strain on the probe head cables 6 Push down the back side of the yellow pincher Insert the probe head resistor lead underneath the center of the yellow pincher and over the center conductor of the deskew fixture The negativ...

Page 356: ...19 Calibrating the Infiniium Oscilloscope and Probe 340 DDR2 LP Compliance Testing Methods of Implementation Figure 44 Solder in Probe Head Calibration Connection Example ...

Page 357: ...nnection 1 On the Infiniium oscilloscope press the autoscale button on the front panel 2 Set the volts per division to 100 mV div 3 Set the horizontal scale to 1 00 ns div 4 Set the horizontal position to approximately 3 ns You should see a waveform similar to that in Figure 45 below Figure 45 Good Connection Waveform Example ...

Page 358: ...and Probe 342 DDR2 LP Compliance Testing Methods of Implementation If you see a waveform similar to that of Figure 46 below then you have a bad connection and should check all of your probe connections Figure 46 Bad Connection Waveform Example ...

Page 359: ...tation 343 Calibrating the Infiniium Oscilloscope and Probe 19 Running the Probe Calibration and Deskew 1 On the Infiniium oscilloscope in the Setup menu select the channel connected to the probe as shown in Figure 47 Figure 47 Channel Setup Window ...

Page 360: ... and Probe 344 DDR2 LP Compliance Testing Methods of Implementation 2 In the Channel Setup dialog box select the Probes button as shown in Figure 48 Figure 48 Channel Dialog Box 3 In the Probe Setup dialog box select the Calibrate Probe button ...

Page 361: ...finiium Oscilloscope and Probe 19 4 In the Probe Calibration dialog box select the Calibrated Atten Offset radio button 5 Select the Start Atten Offset Calibration button and follow the on screen instructions for the vertical calibration procedure Figure 49 Probe Setup Window ...

Page 362: ...cal calibration has successfully completed select the Calibrated Skew button 7 Select the Start Skew Calibration button and follow the on screen instructions for the skew calibration At the end of each calibration the oscilloscope will prompt you if the calibration was or was not successful Figure 50 Probe Calibration Window ...

Page 363: ...loscope channels For infiniium oscilloscopes with bandwidths of 6 GHz and greater use the 54855 61620 calibration cable and the two 54855 64604 precision 3 5 mm adaptors 4 Connect the BNC side of the deskew fixture to the Aux Out BNC of the Infiniium oscilloscope 5 Connect the probe to an oscilloscope channel 6 To minimize the wear and tear on the probe head it should be placed on a support to rel...

Page 364: ...19 Calibrating the Infiniium Oscilloscope and Probe 348 DDR2 LP Compliance Testing Methods of Implementation Figure 51 Probe Calibration Verification Connection Example ...

Page 365: ...of both channels until the waveforms overlap each other 22 Select the Setup menu choose Acquisition from the pull down menu 23 In the Acquisition Setup dialog box enable averaging When you close the dialog box you should see waveforms similar to that in Figure 52 Figure 52 Calibration Probe Waveform Example NOTE Each probe is calibrated with the oscilloscope channel to which it is connected Do not...

Page 366: ...19 Calibrating the Infiniium Oscilloscope and Probe 350 DDR2 LP Compliance Testing Methods of Implementation ...

Page 367: ...sight also recommends the E2677A differential solder in probe head Other probe head options include N5381A InfiniiMax II 12 GHz differential solder in probe head N5382A InfiniiMax II 12 GHz differential browser E2675A InfiniiMax differential browser probe head N5425A InfiniiMax ZIF probe head and N5426A ZIF Tips Figure 53 1134A InfiniiMax Probe Amplifier Figure 54 E2677A N5381A Differential Solder...

Page 368: ...differential solder in probe head provides 10 GHz and 12 GHz bandwidth respectively Table 235 Probe Head Characteristics with 1134A probe amplifier Probe Head Model Number Differential Measurement BW input C input R Single Ended Measurement BW input C input R Differential Solder in E2677A 7 GHz 0 27 pF 50 kOhm 7 GHz 0 44 pF 25 kOhm ...

Page 369: ...0 202 204 206 DQS DQ Skew for DQS and Associated DQ Signals 218 H Half Period Jitter 49 HTML report 28 I in this book 7 InfiniiScan software license 6 Input Signal Minimum Slew Rate Falling 86 88 Input Signal Minimum Slew Rate Rising 82 84 internal calibration 335 K keyboard 6 334 L license key installing 37 M Maximum AC Input Logic High 58 60 62 154 156 158 160 162 164 166 168 Maximum DC Input Lo...

Page 370: ... 36 tJIT duty 49 tJIT per 34 tLZ DQ 216 tLZ DQS 214 tQH 220 tRPRE 236 tRPST 238 240 tWPRE 234 tWPST 232 U User Defined Real Time Eye Diagram Test 331 332 V VID AC 146 VIH AC 58 60 62 102 104 105 106 110 112 114 116 122 124 128 130 131 132 154 156 158 160 162 164 166 168 VIH DC 60 62 154 156 158 160 162 164 166 168 VIL ac 70 72 74 VIL dc 64 66 68 76 78 80 VIX AC 150 VOX 174 W Write Cycle 332 Write ...

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