8
KRF-V6200D/V7200D
Port No.
Port Name
I/O
Explanations
Logic
17
PDN
I
Power-Down and Reset port.
When “L”, the AK4628A is powered-down and the
control registers are reset to default state.
If the state of P/S or CAD1-0 changes, then the
AK4628A must be reset by PDN.
18
TST1
I
Test port.
This port should be connected to DVSS.
-
19
CSD1
I
Chip Address-1 port.
-
20
CAD0
I
Chip Address-0 port.
-
21
LOUT4
O
DAC4 L-ch Analog Output port.
-
22
ROUT4
O
DAC4 R-ch Analog Output port.
-
23
LOUT3
O
DAC3 L-ch Analog Output port.
-
24
ROUT3
O
DAC3 R-ch Analog Output port.
-
25
LOUT2
O
DAC2 L-ch Analog Output port.
-
26
ROUT2
O
DAC2 R-ch Analog Output port.
-
27
LOUT1
O
DAC1 L-ch Analog Output port.
-
28
ROUT 1
O
DAC1 R-ch Analog Output port.
-
29
TST2
I
Test port. This port should be left fl oating or
connected to AVSS.
-
30
NC
-
No Connect.
-
31
LIN
I
L-ch Analog Input port.
-
32
RIN
I
R-ch Analog Input port.
-
33
DZF2
O
Zero Input Detect 2-port.
When the input data of the group 1 follow total 8192
LRCK cycles with “0” input data, this port goes to “H”.
And when RSTN bit is “0”, PWDAN port is “0”, this
port goes to “H”. It always is in “L” when P/S is “H”.
34
VCOM
O
Common Voltage Output port, AVDD/2.
Large external capacitor 2.2uF is used to
reduce power-supply noise.
-
35
VREFH
I
Positive Voltage Reference Input port, AVDD.
-
36
AVDD
-
Analog Power Supply port, 4.5-5.5V.
-
37
AVSS
-
Analog Ground port, 0V.
-
38
DZF1
O
Zero Input Detect 1-port.
When the input data of the group 1 follow total 8192
LRCK cycles with “0” input data, this port goes to “H”.
And when RSTN bit is “0”, PWDAN port is “0”, this
port goes to “H”. Output is selected by setting DZFE
port when P/S is “H”.
39
MCLK
I
Master Clock Input port.
-
40
P/S
I
Parallel/Serial Selection port.
L: Serial control mode, H: Parallel control mode.
41
DIF0
I
Audio data Interface Format 0 port in parallel
control mode.
-
42
DIF1
I
Audio data Interface Format 1 port in parallel
control mode.
-
43
LOOP0
I
Loopback Mode 0 port in parallel control mode.
Enable digital loop-back from ADC to 4DACs.
-
44
TDM0
I
TDM I/F Format Mode port.
L: Normal mode, H: TDM mode.
CIRCUIT DESCRIPTION
