DVR-6100/6100K
13
CIRCUIT DESCRIPTION
Pin No.
Pin Name
I/O
Pin Description
1,12,23
VDD(1~3)
-
Digital positive supplies.
2,13,24
VSS(1~3)
-
Digital ground.
3
XMT958
0
SPDIF transmitter output (unused).
4
WR,DS
I/O
Host Write Strobe, Host Data Strobe, External Memory Write
Enable or General Purpose Input
5
RD,RW
I/O
Host Parallel Output Enable, Host parallel R/W, External
Memory Output Enable, General Purpose Input
6
A1, SCDIN
1
Host address bit one or SPI serial control data input.
7
A0, SCCLK
I
Host parallel address bit zero or serial control pin clock.
8~11
DATA(7~0)
I/O
Data bus (7~0).
14~17
18
CS
I
Chip select input.
19
SCDI0,SCDOUT
I/O
Serial control data input and output.
20
INTREQ ABOOT
I/O
Control pin interrupt request, automatic boot enable.
21
EXTMEM
I/O
External memory chip select input/output.
22
SDATAN
I
PCM audio data input.
25
SCLKN
I/O
PCM audio input bit clock.
26
SLRCLKN
I/O
PCM audio input sample rate clock.
27
CMPDAT
I
PCM audio data input.
28
CMPCLK
I/O
PCM audio input bit clock.
29
CMPREQ
I/O
PCM audio input sample rate clock.
30
CLKIN
I
Master clock input.
31
CLKSEL
I
DSP clock select.
32
FLT2
-
Phase locked loop filter.
33
FLT1
-
Phase locked loop filter.
34
VDDA
-
Analog positive power supply for clock generator.
35
VSSA
-
Analog ground for clock generator PLL.
36
RESET
I
Master reset input.
37
DD
I/O
This pin should be pulled up with an external 4.7k
Ω
resistor.
38
DC
I
This pin should be pulled up with an external 4.7k
Ω
resistor.
39
AUDAT2
O
Digital audio output 2.
40
AUDAT1
O
Digital audio output 1.
41
AUDAT0
O
Digital audio output 0.
42
LRCLK
I/O
Audio output sample rate clock.
43
SCLK
I/O
Audio output bit clock.
44
MCLK
I/O
Audio master clock.
3-11 Digital Audio Decoder : CS493263 (DSP B' D IC33)
4. Block Diagram of Shift Register : BU4094 (Front IC81)
Q's (SERIAL OUTPUT)
Qs (SERIAL OUTPUT)
DATA
CLOCK
STROBE
OUTPUT
ENABLE
8-STAGE
SHIFT REGISTER
8-BIT
LATCHES
3-STATE
4~7, 11~14
Q1
15
1
3
2
10
9
Q8
(PARALLEL OUTPUT)
OUTPUTS
