DV-505/DVF-4050/-S
8
CIRCUIT DESCRIPTION
Pin No.
Pin Name
I/O
Description
38
CLK
I
The system clock input. all other inputs are registered to the SDRAM
on the rising edge of CLK
37
CKE
-
Controls internal clock signal and when deactivated,the SDRAM
will be one of the states among power down, suspend or self refresh.
19
CS
-
Enables or disables all inputs except CLK, CKE, and DQM.
20,21
BA0,BA1
-
Selects bank to be activated during RAS activity.
Selects bank to be read/written during CAS activity.
22~26
A0~A11
-
Row address : RA0~RA11, Column address : CA0~CA7
29~35
Auto-precharge flag : A10
16,17,18
WE,CAS,RAS
-
WE, CAS and RAS define the operation.
15,39
LDQM,UDQM
I/O
Controls output buffers in read mode and masks input data in write mode.
2,4,5,7,8,10
11,13,42,44
DQ0~DQ15
I/O
Multiplexed data input/output pin.
45,47,48,50
1,3,9,14,27
VCC/VCC Q
-
Power supply for internal circuits and input buffers.
43,49
10
VSS/VSS Q
-
Ground terminal.
36,40
NC
-
Unused.
64 Bit SDRAM : HY57V651620B(IC301)
Pin No.
Pin Name
I/O
Description
25,24~16,8~1
A0~A18
I
Address Inputs
29,31,33,35
DQ0~DQ7
I/O
Data Input/Outputs, Command Inputs
38,40,42,44
30,32,34,36
DQ8~DQ14
I/O
Data Input/Outputs
39,41,43
45
DQ15
I/O
Data Input/Outputs or Address input
26
CE
-
Chip Enable
28
QE
-
Output Enable
11
WE
-
Write Enable
12
RP
-
Reset/Block Temporary Unprotect
15
RY/BY
o
Ready/Busy/Output
47
BYTE
-
Byte/Word Organization
37
VCC
-
Supply Voltage
27,46
VSS
-
Ground
Flash Memory : M29F400T-90N1(IC401)
Block Diagram for D/A Converter
BCK
LRCK
DATA
ML
MC
MDI
SCK
Serial
Input
I/F
8X
Oversampling
Digital Filter
with
Function
Controller
Enhanced
Multi-level
Delta-Sigma
modulator
Function
System
Clock
Manager
System Clock
Zero Detect
Power Supply
Control
I/F
DAC
Output Amp and
Low-pass Filter
Vout L
Vout R
Vcom
Output Amp and
Low-pass Filter
DAC
ZERO L
ZERO R
VDD
DGND
VCC
AGND