Keithley KPCI-PIO32IOA, User Manual

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KPCI-PIO32IOA and KPCI-PDISO8A User’s Manual I/O Address Mapping B-3
Register assignments
The KPCI-PIO32IOA and KPCI-PDISO8A registers are mapped shown in Table B-1 .
All offsets from the base address are specified as multiples of four bytes (modulo 4 addressing),
because each offset specifies a four-byte (32-bit) wide register.
NOTE
The term “base” address, as used in the following subsections, does not
have the same meaning for a PCI board, such as the KPCI-PIO32IOA
and KPCI-PDISO8A, as for an ISA board. The base address for your
KPCI-PIO32IOA or KPCI-PDISO8A board is an address BADDR0 that
is mapped in I/O space or BADDR1 that is memory mapped and is
assigned at power-up by the PCI BIOS or the Plug and Play operating
system. It remains constant only as long as the computer is powered. It
is not a fixed, user-assigned I/O address such as 0x300 or 0x310 set on a
DIP switch, nor is it a fixed address such as is assigned for a printer.
Any BADDR that is set to 0x00 has been disabled by system BIOS.
Control and data registers
The control and data register map for the input ports follows. The control port consists of bits
that allow some additional features to implement interrupt control and latching. Both boards
separate the I/O lines into two 32-bit registers. Up to 16-bits of input and output are available on
the KPCI-PIO32IOA, while the KPCI-PDISO8A has 8-bit capabilities.
Register contents are as follows:
The contents of data and control registers may be transferred either 8 bits or 32 bits at a time.
Table B-1
Register mapping
Offset *
(Byte) Content Description
0 Port A Read Only - Input Register (IP0-IP7)
1 Port B Read Only - Input Register (IP8-IP15, KPCI-PIO32IOA only)
2 N/A
3 Control Latching control (R/W)
4 Port A Output Register (R/W) for OP0-OP7
5 Port B Output Register (R/W) for OP8-OP15 (KPCI-PIO32IOA only)
6 N/A
7 N/A
-
34-37 FW Rev ASCII firmware revision, format “AOxx” (Read Only)
38-3A INT CSR Interrupt control register (R/W)
3B N/A
* offset, where I/O mapped is BADDR0, and memory mapped is BADDR1.
Bits of each control and
data register
31.......24 23.......16 15.........8 7.........0
Contents
Control port
(latching only)
Not used Port B Port A