Keithley KPCI-PIO32IOA, User Manual

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KPCI-PIO32IOA and KPCI-PDISO8A User’s Manual External Interrupts 4-3
Data latching
Latching external data is accomplished by first setting up the control register to latch on either a
rising or falling edge. Once the appropriate external edge is received on the INT_REQ line, the
current data value will be latched. The receipt of this external edge will also set the interrupt
pending bit. An actual PCI interrupt will only occur at this time if the interrupts are enabled.
This value will continue to be latched until the control register is written with a non-latching
value. This effectively turns off the latching mode. Input data will not latch regardless of any
INT_REQ edges. This state is the default power up state of the KPCI boards.
If the currently latched value was not acknowledged when the next external edge arrives, new
data will be latched. See the specifications for the register maps containing the locations of the
latch control register and interrupt enable and pending bits.
When data is currently latched, IP6 and IP7 will not be latched. These pins function as
INT_REQ and INT_ENN in addition to digital input lines.
In order to synchronize external data with hardware events represented on the INT_REQ data
line, it is recommended that an interrupt driven programming scheme be used.
External interrupt application
Typically, you would use an external interrupt to ensure that the application program processes,
at a specific time, specific data that are present at one or more ports. You can do so with a board
external interrupt, subject to the following limitations:
• A KPCI-PIO32IOA and KPCI-PDISO8A external interrupt signal signals the driver to
transfer data from whichever port is desired: one, several at once, or several with one per
interrupt. The board provides no way to assign interrupts or intrinsically detect the interrupt
status for a specific bit. (However, you could potentially hardware-set and software-detect
certain I/O bits to tell a custom application program which ports to process for a given
interrupt, or you could compare the current and previous data sets, and then process only
changed data.)
• Conversely, if processing needs and interrupts occur too frequently, data that does need to be
processed can be missed . External interrupt signals are ignored during an interrupt service
routine (ISR) while an interrupt-pending bit is set high—except that the first interrupt miss,
only, does set an interrupt-missed bit.
Therefore, you must 1) know how fast your host computer and application software can process
data, and 2) space important data and interrupts accordingly. Of course, this requirement is not
specific to the KPCI-PIO32IOA and KPCI-PDISO8A boards. It applies to any data acquisition
board. See the specifications in Appendix A for hardware input response times.
You must also ensure, at the end of interrupt-initiated processing, that the application program
resets the interrupt-pending bit, the interrupt-missed bit, and two other bits that recorded
whether the interrupt occurred on the rising or falling edge of the interrupt request signal.
DriverLINX handles this process automatically.