2-2
Functional Description
+5V
+15V
−
15V
Figure 2-1.
Bloc
k Dia
gram of D
AS-TC/B
Address
Decode
Logic
Interr
upt
Control
Logic
Dual-P
or
t
Static
RAM
PC Bus
Static
RAM
RO
M
PC I/O
Decode and
Control
Pulse
Signal
Conditioning
4MHz
Cloc
k
CPU
16MHz
Xtal
CPU
Control
Register
Opto-
Isolator
Opto-
Isolator
V/F
Con
v
e
rter
Opto-
Isolator
Opto-
Isolator
Inst.
Amp
.
Gain
Mux
V
oltage
Ref
.
Input
Mux
Input
Channel
Mux
CH00
CH15
Diff
erential
Input
Channels
00 to 15
CJC Input
+10V
Precision
V
oltage
Ref
erence
DC/DC
Po
w
e
r
Supply
+9.9V
Ref
.
Isolated Input
Section
Control
Section