JYTEK USB-62405, User Manual

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Operation 39
3.4 Programmable Function I/O
The USB-62405 supports powerful programmable I/O function provided
by an FPGA chip, configurable as static digital input/output, 32-bit fre -
quency counters, pulse output, synchronization sample clock IN, and
trigger IN. These signals are single-ended and 3.3 V/ TTL-compliant.
3.4.1 Static Digital Input/Output
Programmable function I/O can be used as static digital inputs or out -
puts, with I/O lines readable and writeable by software polling, with
sample and update rate fully controlled by software timing.
3.4.2 Frequency Counter
Calculates base clocks occurring within a period (rising edge to rising
edge or falling edge to falling edge) of the repetitive input signal, which
is then converted to frequency value. Counter polarity can be adjusted
to rising edge active or falling edge active, with maximum frequency
measurable of 4MHz.
3.4.3 Pulse Output
The GPIO can also simulate a pulse output. By setting a varying amount
of Pulse_initial_cnt and Pulse_length_cnt, varying pulse frequencies and
duty cycles can be obtained. The maximum output frequency is 4MHz,
as shown.
Calculation of the pulse frequency and duty cycle is as follows.
Pulse_initial_count=7 Pulse_length_count=8
Timebase
PWM OUT