| 27
Figure 27 shows a typical channel scan sequence, in which case the user
added some channels in random order under the
“4-wire mdoe” topology.
ADC0
Ch15
ADC1
ADC2
ADC3
Channels added by user
Ch0
Ch2
Ch3
Convert Sequence
time
Sample 0
Ch0
Ch2
Ch3
Ch0
Ch7
Ch2
Ch3
Ch9
Ch15
Ch6
Ch8
Ch7
Ch9
Ch6
Ch8
Ch7
Ch9
Ch6
Ch8
Ch15
Figure 27 Random channel scan sequence
When using the driver, although the scan order of the channels does not
necessarily match the order of adding channels, the data is automatically
reordered internally by the driver, so the order of the data of each
channel’s reading data will always be the same as the order of adding
channels.
5.2.2 ADC Timing Modes
The ADC inside PCIe/PXIe-6301 has a built-in digital filter and multiple
filter options. Filter options affect the data output rate and 50 Hz / 60 Hz
rejection, and the lower the ADC conversion rate, the better the noise
rejection.
The PCIe/PXIe-6301 driver provides a total of 6 ADC convesrion rates,
from Level 0 to Level 5. Level 0 has the slowest conversion rate and best
noise rejection. Level 5 has the fastest conversion rate and lower noise
suppression performance.
The reciprocal of the ADC conversion rate is the time required for each
A/D conversion.
