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3�7 Synchronizing Multiple Modules
The SSI (System Synchronization Interface) of the PXIe-69852 is achieved by a trigger signal, pre_
data_ready signal(s) and a reference clock, all transmitted through PXI_BUS ports to enable multiple
module synchronization. When synchronizing multiple devices, a PXIe-69852 can be configured as a
master or a slave, wherein the system accommodates multiple slave devices but only a single master
device. For better synchronization between multiple devices, all connected PXIe-69852s should refer
to the same time base. The time base can be PXI_CLK 10, PXIe_CLK 100, or an external clock through
the front panel.
When operating in post-trig or delay-trig mode, the only trigger signal transmitted through PXI BUS
is SSI_TRIG1, used to initiate acquisition of all devices. A master device should set one PXI_BUS pin
in output direction. The trigger signal will be sent out through this pin to other slave devices on
PXI_BUS. All slave devices should set the trigger signal from the corresponding PXI_BUS pin so that
all devices on PXI_BUS are triggered simultaneously.
When any device on PXI_BUS is required to operate in pre-trig or mid-trig mode, the master device
must be set correspondingly. The trigger modes of other slave devices are not limited. A slave device
in pre-trig/mid-trig mode transmits a pre_data_ready signal to inform the master device that it is
ready to accept trigger signals (for more details of pre-trig and mid-trig status, please see “PreTrigger
Mode” on page 16. and “Middle Trigger Mode” on page 16.). This slave device should set one PXI_
BUS pin, not used to transmit and receive SSI_TRIG1, to output to transmit its pre_data_ready signal
to master device. If any other slave device is in pre-trig/mid-trig mode, it should set another PXI_BUS
pin to send its pre_data_ready signal. In this scenario, a single line on PXI_BUS is used to transmit
trigger signals from master to slave, while other specified lines are used to transmit pre_data_ready
signals from slave devices in pre-trig/mid-trig mode to a master device. From the master device,
one pin is assigned as output to transmit trigger signal. The trigger signal won’t be sent out until all
slaves’ pre_data_ready is received by the master device.
