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3.3 ADC Sampling Rate and TIMEBASE Control
The PXI/PCI-698X6 supports several timebase sources for analog input conversion:
•
Internal oscillator
• External clock through front panel
• PXI_STAR (PCI version)
• PXI Trigger Bus[0..7] (PXI version)
• PXI 10M (PXI version)
• SSI (PCI version)
The following diagram shows the timebase architecture of the PXI/ PCI-698X6.
8-to
-1
MUX
Ti
m
eb
as
e
Cl
ock
M
ux
PX
I I
nte
rfa
ce
PXI Trigger Bus[0:7]
PXI_STAR
Ext. CLK IN
SMB
Connector
ADC3
PXI
Tr
ig
ge
r Bus
o
r SS
I
PXI_10M
Onboard
Oscillator
ADC0
ADC1
ADC2
8-t
o-
1
M
UX
1-to-5 Clo
ck
Buffer
CLK Buffer
Figure 3-5: PCI/PXI-698x6 Timebase Source and Architecture.
3�3�1 Internal Oscillator
The PCI/PXI-69816/26/46 equips a high stability, low jitter oscillator for the ADCs. The
oscillators are 10 MHz, 20 MHz and 40 MHz for PCI/PXI-69816, PCI/PXI-69826 and PCI/PXI-
69846, respectively.
3.3.2 External Clock Through Front Panel
When you need a specific timebase in some applications that the onboard oscillator is not
achievable, a clock from an external device can replace onboard oscillator. In addition,
external timebase also provides a method to synchronize digitizers to other measurement
modules by distributing/receiving a common clock to/from multiple modules. The PCI/PXI-
69816/26/46 can receive an external timebase from the front panel connector (CLK IN), PXI
STAR or one of the PXI Trigger Bus lines.
You can supply the timebase from external SMB connector CLK IN, which should be a sine
wave or square wave signal. This signal is AC coupled with 50 Ω input impedance and the
valid input level is from 1 to 2 volts peak-to-peak. Note that the external clock must be
continuous for correct ADC operation because of the pipeline architecture of the ADC.
