XV-M565BK/M567GD
1-40
17
16
12
13
14
15
44
1
3
5
2
4
6
7
8
9
10
11
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
DIG7/P7
DIG6/P6
DIG5/P5
DIG4/P4
DIG3/P3
DIG2/P2
DIG1/P1
DIG0/P0
CS
SIN
SOUT
SCLK
VDD
VDD
VSS
RESET
VEE
VEE
XOUT XIN
AN5~AN0
Clock generation
circuit
Noise filter
Noise filter
Trigger
Selector/A-D control circuit
A-D
SIO
Command
analysis
circuit
Byte end
Memory
address
Forwarding
counter
Display RAM
Mode
register
Display control circuit
DIG8/SEG17 DIG17/SEG8
SEG7 SEG0
25
24
23
22
21
20
19
18
3. Block diagram
M35500BGP