JVC XL-SV205GD, Service Manual

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1-6
XL-SV205GD
Pin description
Symbol Pin Name Pin No. Description
D
IN
Data input 6 Inputs serial data at the rising edge of the shift clock, starting from
the low order bit.
D
OUT
Data output 5 Output serial data at the falling edge of the shift clock, starting from
the low order bit. This is the N-ch open-drain output pin.
STB Strobe 9 Initializes the serial interface at the rising or falling edge of the µPD16512.
It then waits for reception of a command. Data input after STB has fallen is
processed as a command. While command data is processed, current
processing is stopped, and the serial interface is initialized. While STB is
high, CLK is ignored.
CLK Clock input 8 Reads serial data at the rising edge, and outputs data at the falling edge.
OSC Oscillator pin 44 Connect a resistor to this pin to determine the oscillation frequency to this
pin.
Seg1/KS1 to High-voltage 15 to 20 Segment output pins (Dual function as key source)
Seg6/KS6 output
Seg7 to seg11 High-voltage 21 to 25 Segment output pins
output (segments)
Grid1 to Grid6 High-voltage 37 to 32 Grid output pins
output (grid)
Seg12/Grid11 to High-voltage 26,28 to 31 These pins are selectable for segment or grid driving.
Seg16/Grid7 output
(segment/grid)
Led to Led Led output 42 to 39 CMOS output. +20 mA max.
Key1 to Key4 Key data input 10 to 13 Data input to these pins is latched at the end of the display cycle.
SW1 to SW4 Switch input 1 to 4 These pins constitute a 4-bit general-purpose input port.
V
DD
Logic power 14, 38 5V ± 10%
V s s Logic ground 7, 43 Connect this pin to system GND.
V
EE
Pull-down level 27 VDD-35 V max.
IC203: PT2399 (ECHO PROCESSOR)
Block diagram