TH-A5R
1-29
1. Pin layout
3. Pin function
2. Block diagram
LC75725E (UIC10) : VFD driver
S8
S7
S6
S5
S4
S3
S2
S1
Vss
OSCO
OSCI
VDD
BLK
CE
CL
DI
VFL
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
VFL
S43
S42
S41
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Symbol
VFL
VDD
Vss
OSCI
OSCO
BLK
CL
DI
CE
G1-G11
S1-S43
Pin No.
1,13
60
57
59
58
61
63
64
62
2-12
56-14
Function
Driver block power supply connection. (Both pins must be connected.)
Logic block power supply connection. Provide a voltage between 4.5 and 5.5V.
Power supply connection. Connect to the ground.
Oscillator connection. An oscillator circuit is formed by connecting an external resistor
and capacitor to these pins.
Display off contort input.
BLK = Low (Vss)...Display off.(S1 toS43 and G1 to G11 at VFL level.)
BLK = High (VDD)...Display on.
Note that serial data can be transferred while the display is turned off.
Serial data transfer inputs. These pins must be connected to the system microcontroller.
CL: Synchronization clock
DI: Transfer data
CE: Chip enable
Digit outputs. These pins are P-channel open drain outputs with pull-down resistors.
Segment outputs for displaying the display data transferred by serial data input. These pin
are P-channel open drain outputs with pull-down resistors.
I/O
-
-
-
I
O
I
I
O
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
DIGIT
DRIVER
SHIFT REGISTER
DIMMRE
TIMING
GENERATOR
ADDRESS
DETECTOR
GRID
CONTROL
TIMING
GENERATOR
DRIVER
CLOCK
GENERATOR
SEGMENT DRIVER
LATCH
MPX
BLK
VFL
G11
G10
G2
G1
DI
CL
CE
Vss
VDD
OSCI
OSCO
S43
S42
S2
S1
Summary of Contents for TH-A5R
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Page 46: ...H A B C D E F G 1 2 3 4 5 2 10 TH A5R TH A5R Main board Forward side ...
Page 47: ...A B C D E F G 1 2 3 4 5 2 11 TH A5R Main board Reverse side ...
Page 51: ...TH A5R 2 15 1 2 3 4 5 A B C D Jack board ...
Page 53: ...TH A5R 3 2 M E M O ...
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