JVC RX-8022PSL, Service Manual, Page: 29 / 78

1-29
RX-8022PSL
UPD784215AGC188 (IC581) : CPU
1. Pin layout
1 ~ 25
75 ~ 51
50
~
26
76
~
100
2. Pin function
Pin No. Symbol Function
1~8
9
10
11
12
13
14
15, 16
17
18
19
20~22
23
24
25
26
27
28
29
30~32
33
34, 35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
VDD
X2
X1
VSS
XT2
XT1
INT0
INT1
DZF
AVDD
AV REF0
CS1
CS2
CS3
CS4
AVSS
AV REF1
RX
TX
DSP COM
DSP STS
DSP CLK
DSP RDY
MISO
MOSI
SCK
HREQ
SS
I/O Pin No. Symbol Function I/O
O
I
I
I
I
I
I
I
I
I
O
I
I
I
O
O
O
O
I
O
I
I
O
I
O
O
I
O
-
+3.0V
Main system clock input
Main system clock input
GND
OPEN
Connect to VSS
Error input1 (ditect UNLOCK)
Error input2 (ditect Non Audio)
GND
The same potential as VDD
The same potential as VSS
Chip select input port
Chip select input port
Chip select input port
Chip select input port
The same potential as VSS
The same potential as VDD
For flash write
For flash write
Command (serial 1)
Status (Serial 1)
Clock (Serial 1)
Ready
Data in (Serial 0)
Data out (Serial 0)
Clock (Serial 0)
HREQ
System slave select
50,51
52
53
54
55
56
57
58~63
64
65
66
67
68
69
70
71
72
73~75
76
77
78
79, 80
81
82, 83
84
85
86
87
88
89~93
94
95~100
DSP_RST
DA_CS
PD_DA
PD
CSTI
CDTO
CCLK
C_CS
DEBUG1
DEBUG2
DEBUG3
GEBUG4
GND
EQ
CTR_TONE
3D
VDD
ANA_TT
LFE_MIX
LFE_CONT
S_MUTE
TEST
O
O
O
O
O
O
O
O
O
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
DSP RESET
Chip select output
Power down output (RESET)
Power down output (RESET)
Data out
Data in
Clock
Chip select output
Debug out port
Debug out port
Debug out port
Debug out port
GND
EQ
Center tone
3D-Phonic
+3.0V
ANALOG./T.TONE
LFE MIX CONTROL
LFE OUT CONTROL
S.MUTE
Usual "VSS"