JVC RM-STHA10EC, Service Manual

Page: 39 / 116

TH-A10R/TH-A10
1-39
Pin NO.
Symbol
I/O
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
O
O
O
O
I
I,O
I,O
I
I
I
I
I
I
I
I
I
I
ATAPI data
ATAPI data
ATAPI data
ATAPI data
ATAPI data
ATAPI data
ATAPI data
ATAPI data
ATAPI data
ATAPI data
ATAPI data
ATAPI data
ATAPI data
ATAPI data
ATAPI data
ATAPI data
ATAPI reset
ATAPI master / slave selection
System control interruption 0
System control interruption 1
System control weight control
System control reset
DASP signal initializing
VSS connection,OPEN
VSS connection, OPEN
VSS connection
System control address
System control address
System control address
System control address
System control address
System control address
System control address
System control address
System control address
System control address
HDD15
HDD0
HDD14
5VDD
HDD1
HDD13
HDD2
VSS
HDD12
VDD
HDD3
HDD11
HDD4
HDD10
5VDD
HDD5
HDD9
VSS
HDD6
HDD8
HDD7
5VDD
NRESET
MASTER
NINT0
NINT1
WAITODC
NMRST
DASPST
VDD
OSCO2
OSCI2
UATASEL
VSS
PVSSDRAM
PVDODRAM
CPUADR17
CPUADR18
VSS
CPUADR15
CPUADR14
CPUADR13
CPUADR12
VDD
CPUADR11
CPUADR10
CPUADR9
MN103007BGA(1/2)
Pin NO.
Symbol
I/O
Function
3.Function
System control address
System control address
System control address
System control address
System control address
System control address
System control address
System control address
GND
System control address
System control chip selection
System control wright
System control lead
Apply 3V
System control data
System control data
C=10000PF is connected
between VSS
VSS connected
System control data
System control data
System control data
GND
System control data
System control data
System control data
16.9/11.2/8.45MHz clock
Apply 3V
Mirror gate
Data part frequency control
switch
Part CAPA switch
RF dropout / BCA data of
making to binary
Outer side CAPA detection
Side of surroundings on inside
GND
VSS connected
System reset
Apply 3V
16.9MHz clock
Frame mark detection
ID gate for tracking holding
Jump prohibition
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
I
I
I
I
I
I
I
I
I
I
I
I
O
I
I/O
I/O
O
-
O
O
O
I
I
I
I
I
-
O
O
O
O
CPUADR8
CPUADR7
CPUADR6
CPUADR5
CPUADR4
CPUADR3
CPUADR2
CPUADR1
VSS
CPUADR0
NCS
NWR
NRD
VDD
CPUDT7
CPUDT6
PVPPDRAM
PTESTDRAM
OVDDDRAM
PVSSDRAM
CPUDT5
CPUDT4
CPUDT3
VSS
CPUDT2
CPUDT1
CPUDT0
CLKOUT1
VDD
TEHLD
DTRO
IDGT
BDO
CPDET2
CPDET1
VSS
MMOD
NRST
VDD
CLKOUT2
PLLOK
IDOHOLD
JMPINH