UX-M55
1-21
1. Terminal layout
2. Pin function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
TEST0
HSO
UHSO
EMPH
LRCK
V
SS
BCK
AOUT
DOUT
MBOV
IPF
SBOK
CLCK
V
DD
V
SS
DATA
SFSY
SBSY
SPCK
SPDA
COFS
MONIT
V
DD
TESIO0
P2Vref
HSSW
ZDET
PDO
I
O
O
O
O
-
O
O
O
O
O
O
I/O
-
-
O
O
O
O
O
O
O
-
I
-
O
O
O
80 51
1 30
100 81
31 50
TC9462F (IC701) : Digital servo single chip processor
Pin No.
Symbol
I/O
Function
UHSO
H
H
L
L
PLAYBACK SPEED
Normal
2 times
4 times
-
HSO
H
L
H
L
Test mode terminal. Normally, keep at open.
Playback speed mode flag output terminal. (Not connect)
Subcode Q data emphasis flag output terminal. Emphasis ON at "H" level and
OFF at "L" level. The output polarity can invert by command. (Not connect)
Channel clock output terminal. (44.1kHz) L-ch at "L" level and R-ch at "H" level.
The output polarity can invert by command. (Not connect)
Digital ground terminal.
Bit clock output terminal. (1.4112MHz) (Not connect)
Audio data output terminal. (Not connect)
Digital data output terminal. (Not connect)
Buffer memory over signal output terminal. Over at "H" level. (Not connect)
Correction flag output terminal. At "H" level, AOUT output is made to correction
impossibility by C
2
correction processing. (Not connect)
Subcode Q data CRCC check adjusting result output terminal. The adjusting
result is OK at "H" level. (Not connect)
Subcode P W data readout clock input/output terminal. This terminal can select
by command bit. (Not connect)
Digital power supply voltage terminal.
Digital ground terminal.
Subcode P W data output terminal. (Not connect)
Playback frame sync signal output terminal. (Not connect)
Subcode block sync signal output terminal. (Not connect)
Processor status signal readout clock output terminal. (Not connect)
Processor status signal output terminal. (Not connect)
Correction frame clock output terminal. (7.35kHz) (Not connect)
Internal signal (DSP internal flag and PLL clock) output terminal. Selected by
command. This terminal output the text data with serial by command. (NC)
Digital power supply voltage terminal.
Test input/output terminal. Normally, keep at "L" level. The terminal that inputted
the clock for read of text data by command.
PLL double reference voltage supply terminal.
2/4 times speed at "VREF" voltage. (Not connect)
1 bit DA converter zero detect flag output terminal.
Phase difference signal output terminal of EFM signal and PLCK signal.
Description of major ICs
