JVC KT-DB1000, Service Manual

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KT-DB1000
9
52 DDOWMSC O Direct data output MSC window output terminal.
53 LVDD1 - Internal digital VDD terminal.
54 VSS3 - Digital VSS terminal.
55~60 DDOMNO0~DDOMNO5 O DIrect data output MSC sub channel ID output terminal.
61 DDOWFIC O Direct data output FIC window output terminal.
62 VDD1 - External digital VDD terminal.
63 VSS4 - Digital VSS terminal.
64 NIRQ O Interllupt request output terminal.
65 MPUTX O MPU interface serial data output terminal.
66 MPURX I MPU interface serial data input terminal.
67 MPUCLK I MPU interface serial clock input terminal.
68 NMPUEN I MPU interface chip enable input terminal.
69 MPUMOD I MPU interface mode signal input terminal.
70 MDSPMO0 O MDSP status monitor output 0 terminal.
71 MDSPMO1 O MDSP status monitor output 1 terminal.
72 MVDD0 - DRAM VDD terminal.
73 MVSS0 - DRAM VSS terminal.
74 MDSPMO2 O MDSP status monitor output 2 terminal.
75 MDSPMO3 O MDSP status monitor output 3 terminal.
76~79 SDSPMO0~SDSPMO3 O SDSP status monitor output terminal.
80 MVDD1 - DRAM VDD terminal.
81 MVSS1 - DRAM VSS terminal.
82 VSS5 - Digital VSS terminal.
83 LON - Internal onchip power switch input terminal.
84 VDD2 - External digital VDD terminal.
85 VDD3 - External digital VDD terminal.
86 VOUT0 - Onchip power supply output terminal.
87 VOUT1 - Onchip power supply output terminal.
88 NRST I Master reset input terminal.
89 MCLKEN I Master clock enable input terminal.
90 MCLK24 I Mster clock input terminal.(24.576 MHz)
91 MCLKO O Master clock oscillation output terminal.
92 PWMVCXO O PWM output terminal for mastewr clock VCXO.
93 LVDD2 - Internal digital VDD terminal.
94 VSS6 - Digital VSS terminal.
95~100 TEST0~TEST5 I Test mode setting terminal.
Pin No. Symbol I/O Function
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