2.Pin function
PIN No.
1
2
3
SYMBOL
TEST0
HSO
UHSO
I/O
I
O
O
FUNCTIONAL DESCRIPTION
Test mode terminal.Normally, Keep at open.
Playback speed mode fllag output terminal.
Subcode Q data emphasis flag output terminal.Emphasis ON at "H" level
and OFF at "L"level.The output polarity can invert by command.
Channel clock output terminal.(44.1khz)L-ch at "L" level and R-ch at
"H" level. the output polarity can invert by command.
REMARKS
With pull-up resistor.
UHSO
H
H
L
L
HSO
H
L
H
L
PLAYBACK SPEED
Nomal
2 times
4 times
--
Digital GND terminal.
Bit clock output terminal.(1.4122MHz)
Audio data output terminal.
Digital data output terminal.
Buffer memory over signal output terminal. Over at "H" level.
Correction flag output terminal. At "H" level,AOUT output is made to
correction impossibility by C2 correction processing.
Subcode Q data CRCC check adjusting result output terminal.
The adjusting result is OK at "H" level.
Subcode P~W data reabout clock input/output terminal.
This terminal can select by command bit.
Digital power supply voltage terminal.
Digital GND terminal.
Subcode P~W data output terminal.
Subcode block sync signal output terminal.
Processor status signal reabout clock output terminal.
Processor status signal output terminal.
Correction frame clock output terminal. (7.35kHz)
Internal signal (DSP internal flag and PLL clock) output terminal.Selected
by command.This terminal output the text data with serial by command.
Digital power supply voltage terminal.
Play-back frame sync signal output terminal.
4
5
EMPH
LRCK
O
O
6
7
8
9
10
11
VSS
BCK
AOUT
DOUT
MBOV
IPF
--
O
O
O
O
O
12
13
SBOK
CLCK
O
I/O
14
15
16
17
18
19
20
21
22
VDD
VSS
DATA
SFSY
SBSY
SPCK
SADA
COFS
MONIT
--
--
O
O
O
O
O
O
O
23
24
VDD
TESIO0
--
I
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
LPF amplifier inverting input terminal for PLL.
LPF amplifier output terminal for PLL.
PLL reference voltege supply teminal.
VCO center frequency reference level terminal.
Normally, keep at "PVREF" level.
VCO filter terminal.
Analog power suppyl coltage terminal.
31
32
33
34
--
I
39
AVDD
--
Analog input.
Analog output.
--
--
--
25
26
27
28
PLL double reference voltage supply terminal.
Test input/output terminal.Normally,keep at "L" level.
The terminal that inputted the clock for read of text
data by command.
P2VREF --
HSSW
ZDET
PDO
O
O
O
O
O
2/8 times speed at "VREF" voltage.
1bit DA converter zero detect flag output terminall.
Phase differnce signal output terminal of EFM signal
and PLCK signal.
TMAX detection result output terminal. Selected by
command bit (TMPS).
TMAX detection result output terminal. Selected by
command bit (TMPS).
DIFFERENCE RESULT
Longer than fixed freq.
Shorter than fixed freq.
Within the fixed freq.
TMAX OUTPUT
"P2VREF"
"VSS"
"Hiz"
PVREF
VCORE
AVSS
I
O
35
VCOF
O
--
36
2-state output.(PVREF,Hiz)
3-state output.
(P2VREF,PVREF,VSS)
3-state output.
(P2VREF,PVREF,VSS)
3-state output.
(P2VREF,Hiz,VSS)
Analog output.
Analog output.
Analog input.
Analog input.
Analog GND terminal.
37
38
SLCO
O Data slice level output terminal.
RFI
I
RF signal input terminal.
40
Analog output. (Zin:50k)
Analog input.
Analog input. (Zin:
selected by command)
41
42
43
RFCT
RFZI
RFRP
FEI
I
I
I
I
RFRP signal center level input terminal.
RFRP zero cross input teminal.
RF ripple signal input terminal.
Forcus error signal input terminal.
Analog output.
1-28
KD-SX870
KD-SX770
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9
8
TEL 13942296513
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