1-34
KD-SX787
Pin No.
42
41
40
7
8
9
36
35
34
13
14
15
45
44
43
39
38
37
21
10
11
12
5
4
6
28
33
16
32
17
31
30
18
19
57
56
27
29
22
23
20
26
25
24
LF1C1
LF1C2
LF1C3
RF1C1
RF1C2
RF1C3
LF3C1
LF3C2
LF3C3
RF3C1
RF3C2
RF3C3
NC
TEST
LTOUT
RTOUT
LFIN
RFIN
LFOUT
LROUT
RFOUT
RROUT
Vref
VDD
DVSS
LAVSS
RAVSS
MUTE
TIM
CL
DI
CE
The capacitor connection terminal of the filter composition for the F1 stap of the equalizer.
LF1C1(RF1C1)~LF1C2(RF1C2),Connect the capacitor for LF1C2(RF1C2)~LF1C3(RF1C3).
Capacitor connection terminal of filter composition for F3 strap of equalizer.
Connect the capacitor for LF3C1(RF3C1)~ LF3C2(RF3C2)
LF3C2(RF3C2)~LF3C3(RF3C3).
No connected
The terminal only fot the test of LSI.Connects with GND and uses usually.
Equalizer output terminal.
The fader block input terminal.
Drive by low impedance.
The fader output terminal.A rear reception desk side / side can be separately narrowed
respectively.
L/R of the amount of attenuation is the same.
VDD/2voltage generation part.
Connect the capacitor of about several 10 F as a counter measure for ripple of power
supply between Vref~AVSS for (VSS).
Power supply terminal.
System logic grand terminal.
Analog grand terminal.
External control mute terminal.
When this terminal is made VSS level,fader volume block is set in compulsory-
Timer terminal at no signal of 0 crossing circuit.
Cereal data and clock input terminal for control.
chip enable terminal.
[H]data is written in an internal latch in the timing which becomes [L]and an analog
each switch moves.[H] The data transfer becomes enable at the level.
Symbol
Function
LC75412W
