1-46 (No.49841)
4.13 MN102H60KCJ1 (IC801) : LCD display sub CPU
• Pin layout
• Block diagram
1
25
26
50
75
51
100
76
Pin No.
Symbol
I/O
Function
1
RES
O
LCD reset output
2
RE
O
Read enable output for extension memory
3
WE
O
Write enable output for extension memory
4
VCCWCNT
O
Writing voltage control for external ROM
5
RY/BY
I
Read/Busy input for extension memory
6
CS0
O
Chip select1 output for extension memory
7
NC
-
Connect to ground
8
SWLED4
O
SW_LED flashing output 4 for [PRESET1-6] key LED
9
SWLED5
O
SW_LED flashing output 5 for [[SEEKDOWN] key LED
10
SWLED6
O
SW_LED flashing output 6 for [[DISCDOWN] key LED
11
NC
-
Connect to ground
12
WORD
I
Bus width setting for extension memory (H: 8-bit width)
13 to 16
A0 to A3
O
Extension memory output 0 to 3
17
VDD
-
Power supply
18
NC
O
Not use (Base clock output)
19
VSS
-
Ground
20
XI
I
Connect to ground
21
XO
O
Not connect
22
VDD
-
Power supply
23
OSCI
I
Crystal connecting terminal (25MHz)
24
OSCO
O
Crystal connecting terminal (25MHz)
Mode setting input, pull up (H: memory extension mode)
Extension memory output 4 to 11
Analog power supply
Extension memory output 12 to 19
Analog reference power supply, connect to ground
Extension memory output 20
Audio level input for spectrum analyzer
47
WDOUT
O
Watch dog timer over flow output (H: over flow)
48
PON
O
Power on output
49
RD
O
LCD read strobe output
50
LCDCLK
O
LCD driver clock output (300kHz)
51
WR
O
LCD write strobe output
52,53
NC
-
Not connect
54
AVDD
-
Analog reference power supply, connect to AVDD
55
RS
O
LCD regist select output
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