KD-SH77R/KD-SH55R
1-20
TC9490FA (IC621) : DSP
1. Pin layout & Block diagram
2. Pin function (1/2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
O
O
O
O
O
-
-
O
I/O
O
O
O
O
O
-
O
O
I
O
-
O
-
O
I
-
Bit clock output pin.32fs, 48fs, or 64fs selectable by command.
L/R channel clock output pin. "L" for L channel and "H" for R channel.
Audio data output pin. MSB-first or LSB-first selected by command.
Digital data output pin. Outputs up to double-speed playback.
Correction flog output pin.
Digital 3.3V power supply voltage pin.
Digital GND pin.
Subcode Q data CRCC result output pin. "H" level when result is OK.
Sub-code P-W data read clock I/O pin. I/O polarity selectable by command.
Sub-code P-W data output pin.
Playback frames sync signal output pin.
Sub-code block sync output pin.
Playback speed mode flag output pin.
Playback speed mode flag output pin.
PLL-only 3.3V power supply voltage pin.
EFM and PLCK phase difference signal output pin.
TMAX detection result output pin.
Inverted input pin for PLL RF amp.
Output pin for PLL LPF amp.
PLL-only VREF pin.
VCO filter pin.
Analog GND pin.
DAC output pin for data slice level generation.
RF signal input pin.
Analog 3.3V power supply voltage pin.
BCK
LRCK
AOUT
DOUT
IPF
VDD3
VSS3
SBOK
CLCK
DATA
SFSY
SBSY
/HSO
/UHSO
PVDD3
PDO
TMAX
LPFN
LPFO
PVREF
VCOF
AVSS3
SLCO
RFI
AVSS3
No.
Symbol
I/O
Function
49
DV
DV
SS3
V
SS5
V
DD5
DD3
DD3
RO
V
DD3
V
SS3
PV
DD3
BCK
LRCK
A
OUT
DOUT
IPF
SBOK
CLCK
D
ATA
SFSY
SBSY
/HSO
/UHSO
PDO
DVR
LO
ZDET
BUS0
BUS2
BUS3
BUCK
/CCE
/RST
BUS1
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
DV
32 TEZI
TEI
SBAD
FEI
RFRP
RFZI
RFCT
RFI
SLCO
VCOF
LPFO
LPFN
TMAX
AV
DD3
AV
SS3
PV
REF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
XO
XI
TESIN
DMO
FMO
SEL
TEBC
RFGC
TR
O
FOO
XV
DD3
XV
SS3
AV
DD3
V
DD3
V
SS3
V
REF
Clock
generator
LPF
1-bit
DAC
16 k
RAM
Address
circuit
Correction
circuit
Audio output
circuit
Micro-
controller
interface
Digital output
Sub code
decoder
PLL
TMAX
VCO
Sync signal
protection
EFM
CLV servo
Data
slicer
A/D
D/A
Servo control
ROM
RAM
Digital equalizer
automatic
adjustment circuit
PWM
Description of major ICs
Summary of Contents for KD-SH55R
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