1-22
KD-S723R/KD-S721R
2.Pin function
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
70
69
68
-
+
-
+
LPF
1bit
DAC
Clock
generator
Servo
control
PWM
D/A
A/D
Digital equalizer
Automatic adjustment
circuit
ROM
RAM
CLV servo
Address circuit
Micon
interface
Correction
circuit
Audio out
circuit
16KRAM
Digital out
Sub code
decoder
Status
Synchronous
guarantee
EFM decode
PLL
TMAX
VCO
Data
slicer
TC9462F(IC541):DSP&DAC
1.Pin layout & Block Diagram
PIN No.
1
2
3
SYMBOL
TEST0
HSO
UHSO
I/O
I
O
O
FUNCTIONAL DESCRIPTION
Test mode terminal.Normally, Keep at open.
Playback speed mode flag output terminal.
Subcode Q data emphasis flag output terminal.Emphasis ON at "H" level and OFF at "L"
level.The output polarity can invert by command.
Channel clock output terminal.(44.1khz)L-ch at "L" level and R-ch at "H" level. the output
polarity can invert by command.
REMARKS
With pull-up resistor.
UHSO
H
H
L
L
HSO
H
L
H
L
PLAYBACK SPEED
Nomal
2 times
4 times
--
-
+
-
+
Digital GND terminal.
Bit clock output terminal.(1.4112MHz)
Audio data output terminal.
Digital data output terminal.
Buffer memory over signal output terminal. Over at "H" level.
Correction flag output terminal. At "H" level,AOUT output is made to correction
impossibility by C
2
correction processing.
Subcode Q data CRCC check adjusting result output terminal.
The adjusting result is OK at "H" level.
Subcode P W data readout clock input/output terminal.
This terminal can select by command bit.
Digital power supply voltage terminal.
Digital GND terminal.
Subcode P W data output terminal.
Subcode block sync signal output terminal.
Processor status signal readout clock output terminal.
Processor status signal output terminal.
Correction frame clock output terminal. (7.35kHz)
Internal signal (DSP internal flag and PLL clock) output terminal.Selected by command.
This terminal output the text data with serial by command.
Digital power supply voltage terminal.
PLL double reference voltage supply terminal.
Test input/output terminal.Normally,keep at "L" level.
The terminal that inputted the clock for read of text data by command.
Play-back frame sync signal output terminal.
14
15
16
17
18
19
20
21
22
V
DD
V
SS
DATA
SFSY
SBSY
SPCK
SPDA
COFS
MONIT
--
--
O
O
O
O
O
O
O
23
24
V
DD
TESIO0
--
I
25
P2V
REF
--
--
--
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--
--
--
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9
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9
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8
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9
2
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4
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9
8
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5
1
5
1
3
6
7
3
Q
Q
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