1-32
KD-LH1000
LPF
1-bit
DAC
Clock
generator
Micro-
controller
interface
Audio out
circuit
Digital
output
Address
circuit
Correction
circuit
16 k
RAM
CLV servo
Digital equalizer
automatic
adjustment circuit
Servo
control
A/D
D/A
PWM
Synchronous
guarantee
EFM
decoder
Sub code
decoder
PLL
TMAX
VCO
Data
slicer
ROM
RAM
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
6
7
8
9
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
TC94A14FA (IC621) : D.SURVO & DSP
1.Terminal layout & block daiagram
Descroption
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12
13
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15
V
DD3
V
SS3
SBOK
CLCK
DATA
SFSY
SBSY
HSO
UHSO
PV
DD3
-
-
O
O
O
O
O
I/O
-
Bit clock output pin.32fs,48fs,or 64fs selectable by command.
L/R channel clock output pin."L" for L channel and "H" for R channel. Output polarity
can be inverted by command.
Audio data output pin. MSB-first or LSB-first selectable by command.
Digital data output pin.Outputs up to double-speed playback.
Correction flag output pin. When set to "H", AOUT output cannot be corrected by C2
Digital 3.3V power supply voltage pin.
Digital GND pin.
Subcode Q data CRCC result output pin. "H" level when result is OK.
Subcode P-W data read I/O pin. I/O polarity selectable by command.
Subcode P-W data output pin.
Playback frame sync signal output pin.
Subcode block sync signal output pin. "H" level at S1 when subcode sync is detected.
General-purpose input / output pins.
Input port at reset.
PLL-only 3.3V power supply voltage pin.
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