JVC HR-V210EX, Schematic Diagrams

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2-31 2-32
START_SENSOR
START
SENSOR
Q3001
76
END_SENSOR
END
SENSOR
Q3002
85
+5V
(32kHz)
CTL(+)
CTL(-)
MAIN (SYSCON)
REC_SAFETY
CTL_AMP_OUT
TO
D.FF
CN2001
2 1
LSD
SYNC_IN
VIDEO SECTION (ON SCREEN)
V TO OSD
V FROM OSD
V. PULSE V. PULSE
VIDEO/N. AUDIO
VIDEO_ENV
MESECAM_DET
VIDEO_ENV
MESECAM_DET
SECAM(H)
X3002
TIMER CLOCK
SW SAFETY REC S3001
SDA
SCL
5
6
(SYSTEM CONTROL MICRO PROCESSOR)
IC3001
LSB
LSD
LSC
TP4001
CTL. P
3 0
LSB
LSA
LSC
ENCODER
ROTARY
1
2
CN1
( + ) HEAD CTL
( - ) HEAD CTL
CTL
HEAD A/C
A/C HEAD
VIDEO/N. AUDIO
TO
23
24
50
49
47
D.FF
76
75
74
41
40
XC_OUT
XC_IN
X3001
MAIN SYSTEM
CLOCK
(14MHz)
37
38
X_OUT
X_IN
I2C_DATA_AV
I2C_CLK_AV I2C_DATA
I2C_CLK
IC3003
(SERIAL MEMORY)
21
27
A.MUTE(H)
N.REC ST(H)
N.REC(H) N.REC(H)
12C_CLK2
N.REC_ST(H)
A.MUTE(H)
A.MUTE(H)
TO
VIDEO/N. AUDIO
WF5
WF6
TO
FMA
TO
VPS/PDC_SLICER
TO
TUNER
TO
TERMINAL
C.FG_IN
CAP.M_F/R
CAP_CTL_V
LM_F/R/S
D.FG_IN
DRUM_CTL_V
68
62
33
61
65
34
22
17
18
15
31
32
I2C_DATA2
I2C_CLK2
H.REC_ST(H) H.REC_ST(H)
28
PAL_PB(H) PAL_PB(H)
80
V_TO_OSD
VIDEO_OSD_OUT
WF3
WF4
83
84
S_DET S_DET
30
92
93
LSA
91
94
CN3002
3
4
2
5
5
6
1
4
9
10
11
12 12
10
4
11
9
1
5 7
CAP MDA/DRUM
MOTOR
M
CAP.M FG
CAP.M F/R
CAP.M VCTL
LM F/R/S
DRUM PG/FG
DRUM CTL
CN3001
WF1
WF2
PHOTO
SENSOR
PHOTO
SENSOR
PC3001
PC3002
1
2
SP FG
TU FG
12C_DATA2
12C_CLK2
12C_DATA2
+
SYSTEM CONTROL BLOCK DIAGRAM