1
2
3
5
4
A
B
C
D
E
F
G
H
DSP SCHEMATIC DIAGRAM
4.10
4-22
4-21
C4303
R4346
CLK4M5
IRIS_PWM
S_SHUT
VGAT
XAHD
XAVD
MVD
REG_2.5V
(NC)
REG_4.8V
R4339
R4340
R4305
R4306
TL4313
R4345
R4344
CRWSEL
VDCVF
CDSTB
CALE
BUS15
BUS14
BUS13
BUS12
BUS11
BUS10
BUS9
BUS8
BUS7
BUS6
BUS5
BUS4
BUS3
BUS2
BUS1
BUS0
DSP_RST
R4343
TL4306
OMT
TL4309
MFLD
CLK27
CLK18
CLK13
ID
DYI3
IC4304
R4342
CAM_VD
TDO
DA_B
DV_C
DV_Y
INH
INV
DCO0
DCO1
DCO2
DCO3
DYO0
DYO1
DYO2
DYO3
DYI2
DYI1
DYI0
DCI3
DCI2
DCI1
DCI0
OUTH
OUTV
R4347
C4317
L4307
R4348
BLKC
ATF_GAIN
TL4350
R4349
GND
REG_1.8V
REG_3V
L4301
R4350
R4303
R4304
R4351
TRST
TCMK
L4303
C4304
TMS
R4307
R4311
R4312
R4313
R4310
R4309
C4323
C4324
C4310
C4316
C4319
TL4314
L4304
C4314
C4312
C4315
C4307
C4313
TDB
PBVCOCTL
PBLK
OBCLP
L4305
TL4305
TL4304
C4320
C4321
C4318
L4306
IC4202
C4305
RECCADJ
PBPLLCTL
HDCVF
HRP
C4349
C4308
C4306
C4214
CDS_CS
CLK_OUT
C4348
C4347
C4301
C4346
C4345
C4344
C4343
C4341
C4340
C4339
C4338
C4337
C4336
C4335
C4331
DATA_OUT
TL4351
AD_CLK
TL4316
TL4405
TL4353
TL4310
TL4354
TL4352
TL4317
C4202
SHD
SHP
R4341
H_OFFSET
VC0
VC1
VC2
DUMP_CTL
TL4312
R4308
BLKA
DA_R
R4205
R4301
C4342
NOSIG_LV
R4338
FSPLLCTL
M_VCOCTL
R4315
TL4308
IC4301
R4206
DA_G
VC3
BLKB
DOT_CLK
OSD_VD
OSD_HD
R4335
R4333
R4334
R4336
C4325
C4326
C4329
C4327
C4328
L4201
L4302
C4350
R4314
C4309
C4311
R4337
R4202
IC4201
C4215
C4216
C4210
C4212
C4211
C4213
C4206
C4207
TL4307
TL4311
R4207
R4208
R4201
C4204
C4203
C4208
C4205
C4209
TL4202
C4217
TL4303
TL4302
C4201
R4203
CN107
TL4201
H_GAIN
TL4301
IC4302
RA4301
RA4302
RA4303
C4333
C4334
0.1
0
Ω
0
Ω
0
Ω
0
Ω
0
Ω
0
Ω
22K
0.1
10
µ
22K
22K
22K
22K
10
µ
0.1
33k
12k
2.7k
2.7k
0
Ω
0.1
10
10
0.1
22
µ
0.1
0.1
10
10
22
0.1
0.1
0.1
10
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
10
0.1
0
Ω
6.8k
33K
0
Ω
0.1
22
10k
1k
0
Ω
0
Ω
0.1
0.1
0.1
0.1
0.1
12k
0.1
1
0
Ω
0
Ω
0.1
0.1
0.1
0.1
0.1
0.1
1
0.1
1k
1k
0.1
1
0.1
0.1
1
0.1
100
0
Ω
100
100
100
0.1
0.1
VOUT
GND
NOISE
VIN
CONT
∗
NQR0129-002X
/6.3
/6.3
/6.3
/6.3
/6.3
NQR0129-002X
NQR0129-002X
V
OUT
GND
NOISE
VIN
CONT
MM1385HN-X
/6.3
/6.3
VDDI
VSS
DCI0
DCI1
DCI2
DCI3
OUTH
OUTV
VDDI
VSS
ADDVDDE
CLK27
CLK18
CLK13
ID
VDTG
HDTG
LHFO
ADDVDDE
VSS
ADDVDDE
ADDVSS
VDDI
ADIN0
ADIN1
ADIN2
ADIN3
ADIN4
ADIN5
ADIN6
ADIN7
ADIN8
ADIN9
MCLK
IE1
FMWE1
WA
D
RAD
FMRE1
RAE1
FMWR
W
AE1
VDDI
VSS
ADD
V
DDE
IE2
FMWE2
FMRE2
RAE2
W
AE2
TMY0
TMY1
TMY2
TMY3
TMY4
TMY5
TMY6
TMY7
TMC0
TMC1
TMC2
TMC3
ADD
V
DDE
ADD
V
SS
FMY0
FMY1
FMY2
FMY3
FMY4
FMY5
FMY6
FMY7
FMC0
FMC1
FMC2
FMC3
VDDI
VSS
DACTEST
AVDDA
AVSSA
VREFHK
VREFLK
K_OUT
IREFVF
VREFVF
B-Y_OUT
R-Y_OUT
IREFC
VREFC
C_OUT
IREFY
VREFY
Y_OUT
Y2_OUT
NC
PBLK
RE/RW
WE/DSTB
ALE/ASTB
BUS15
BUS14
BUS13
BUS12
BUS11
BUS10
BUS9
BUS8
BUS7
BUS6
BUS5
BUS4
BUS3
BUS2
BUS1
BUS0
CLR
VDCPU
HDCPU
FRP
OMT
AFBEND
FLDCPU
BEND
VSS
GT_X
VPD
CS
GT_S
TDOUT
TDIN
TRST
TMS
TCK
CPUSEL1
CPUSEL0
TVSEL
DSCI7
DSCI6
DSCI5
DSCI4
VDDI
VDMD
A
PWM
CLK45
CLKOSD
HDOSD
VDOSD
BLK1
BLK2
VC1
VC2
VR
VG
VB
VBLK
DSYI0
DSYI1
DSYI2
DSYI3
DSYI4
DSYI5
DSYI6
DSYI7
DSCI0
DSCI1
DSCI2
DSCI3
FLDDSC
VDDSC
HDDSC
CLKDSC
DSCO7
DSCO6
DSCO5
DSCO4
DSCO3
DSCO2
DSCO1
DSCO0
DSY
O7
DSY
O6
DSY
O5
DSY
O4
DSY
O3
DSY
O2
DSY
O1
DSY
O0
ADD
VDDE
VSS
VSS
ADDVSS
DY
I3
DY
I2
DY
I1
DY
I0
INV
INH
DCO3
DCO2
DCO1
DCO0
VDDI
VSS
DYO
3
DYO
2
DYO
1
DYO
0
ADD
VSS
VDDI
VSS
ADDVDDE
CSYNCI
HD
ANA
VD
ANA
ANA
C
NT
AY
O
0
AY
O
1
AY
O
2
AY
O
3
A
CO0
A
CO1
A
CO2
A
CO3
INHA
INV
A
NC
DVDDM
VDDI
VDDI
VSS
DVDDM
AVDDV1
AVDDV2
AVSSV1
AVSSV2
AVDDE1
AVDDE2
AVDDE3
AVSSE1
AVSSE2
AVSSE3
VREFH1
VREFH2
VREFH3
VREFL1
VREFL2
VREFL3
EOUT1
EOUT2
EOUT3
EOUT4
EOUT5
EOUT6
EOUT7
EOUT8
EOUT9
EOUT10
EOUT11
EOUT12
SCBLK
O
ADDVDDE
ADDVSS
ADDVDDE
VSS
VDDE
VSS
VDDE
VSS
ADDVDDE
ADDVSS
ADDVDDE
VDDE
VDDE
ADD
VDDE
VDDE
VDDE
VDDE
GT_B
GT_A
HRP2
HRP1
HDCVF
VDCVF
ADD
V
SS
ADD
V
SS
ADD
V
SS
ADDVSS
JCY0158
NQR0129-002X
NQR0129-002X
NC
D0
D1
D2
D3
NC
D4
D5
D6
D7
D8
D9
SCK
SD
A
T
A
VRM
DV
D
D
DV
S
S
SPSIG
CDSIN
CS
D
V
SS
DV
D
D
DRD
VDD
VRB
ADCIN
AVSS
BLKC
VR
T
DV
S
S
NC
AVSS
AVDD
BLKSH
BLKFB
BIAS
AVDD
NC
AVSS
OEB
DV
D
D
DV
D
D
DV
S
S
OBP
PBLK
DV
D
D
DV
D
D
ADCLK
SPBLK
HD49334F
/4
CCD_OUT
VSS
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
RCLK
RXAD
RADE/RX
RR
RXINC
RE
OE
DO0
DO1
VCC
DO2
DO3
VSS
DO4
DO5
V
CC
DO7
DO6
VSS
DO8
DO9
VCC
DO10
DO11
IE
WXINC
WE
WR/TR
W
ADE/RX
WXAD
WCLK
DIN11
DIN10
DIN9
DIN8
DIN7
DIN6
MSM548331T
A
NRZ0034-101W
NRZ0034-101W
NRZ0034-101W
∗
∗
#
#
∗
T
T
T
T
T
T
∗
∗
∗
#
T
[FILED_MEMOR
Y]
[FILED_MEMORY]
[3V_REG.]
[2.5V_REG.]
∗
R4302
R4303
NTSC
PAL
0
Ω
0
Ω
∗
[FILED_MEMOR
Y]
∗
&SSG
#Difference Point
∗
CVF_OUT
[FILED_MEMORY]
KIZU
CPU
I/F
DSC
I/F
SELECT
Y/C
HNR
IWD
OSD
I/F
ANA
I/F
EIS
FMC
AUTO
DVC
I/F
ENC
SENC
OSD_IF
CPU_IF
D
A
C_ENC_OUT
AD_CONV_IN
MEMORY_IN
[L:NT_H:PS]
[L:N_H:M]
[L:MN2_H:MN3]
DSC_OUT
DSC_IN
ANALOG_IN
[CAMERA_DSP]
EVR
CDS
TG_IF
PGA
CVF
EVR
DAC
Y
DAC
DAC
DAC
DAC
DAC
DAC
C
GY
RY
BY
K
KASHA
CONTROL
CLK
GEN
MEMORY_OUT
DVC_IN
DVC_OUT
[CDS/AGC/AD]
10bit
ADC
I/F
TIMING
GEN
TO TG
TO CCD
CN5001
TO
SYSCON
TO D.CPU,
OP.DRV
TO OP.DRV
TO DVMAIN
NOTE : The parts with marked ( ) is not used.
∗
y10273001a_rev0
TO REG
TO MONI IF
TO V OUT
TO AUDIO
TO PRE/REC
TO PRE/REC
TO PRE/REC
TO DVMAIN
TO DVMAIN
TO DVMAIN
TO OP.DRV
TO DVMAIN
TO DVMAIN
TO
MAIN IF CN101
TO SYSCON, DVMAIN
0 1 MAIN (DSP)
When ordering parts, be sure to order according to the Part Number indicated in the Parts List.
For the destination of each signal and further line connections that are cut off from
this diagram, refer to "4.1 BOARD INTERCONNECTIONS".
NOTES :
