JVC GR-D350UC, Schematic Diagrams

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(No.YF123)2-15 2-16(No.YF123)
IC3701
BH7612FV-X
OPEN
IC3702
NJM2562F1-X
DCO2
R3706
OPEN
R3704
OPEN
TL3201
REG_4.8V
L3203
NQR0602-001X
DCO1
DYO1
VC1
CLK27A
DCO0
C3709
OPEN
L3204
10u
L3201
NQR0602-001X
R3707
OPEN
OSD_HD
VOI_CLK
R3701
150
Q3701
OPEN
DYO2
DOT_CLK
R3709
OPEN
T_F_V_RST
C3213 0.1
LCD_B
ASPECT
C3206 0.01
VC0
C3706
OPEN
C3707
OPEN
R3713
OPEN
R3201 100
DCO3
T
C3204
10/6.3
VC3
LCD_R
R3202
27k
R3703
OPEN
VIF_CS
VOI_IN
DYO3
D3701
UMZ6.8EN-W
OPEN
1 2 3
4 5
ANA_IN_H
GND
T C3711
OPEN
REG_3.1V
T
C3712
100/4
C3212 0.1
OUTH
VOI_OUT
BLKB
R3715
OPEN
C_OUT
PSCTL
C3210 0.1
REG_1.7V
L3202
NQR0602-001X
BLKA
R3708
68
C3207 0.01
C3215 0.1
LCD_G
R3203
15k
T
C3713
OPEN
C3202
0.1
L3701
10u
T
C3710
22/4
BLKC
C3203
0.1
VC2
Q3704
2SA1774/QR/-X
OPEN
R3208
820
DYO0
Q3702
UMZ1N-W
OPEN
5
4 6
2
1 3
OUTV
VDCVF
R3712
OPEN
OSD_VD
HDCVF
V_OUT
Y_OUT
R3714
OPEN
HRP
16
GND
15
VCC
14
YIN
13
PSCTL
12
GND
11
YOUT
10
YSAG
9
PVCC
1
CIN
2
GND
3
SDCIN
4
SDCOUT
5
COUT
6
MIXOUT
7
MIXSAG
8
PGND
C3708
OPEN
R3204
820
C3714
OPEN
1 PSCTL
2 VOUT
3 VSAG 4 VIN
5 GND
6 VCC
R3719
0 '
C3717
0.1
IC3201
JCP8055FP-2
1 HDCVF
2 VDCVF
3 CSYNC
4 VDOUT
5 SCANMODE
6 VDD(C)
7 VSS
8 RESVD
9 RESHD
10 SDOUT
11 SDIN
12 SCLK
13 CS
14 VDD(I)
15 VSS
16 RST
17
CLK
18
VC0
19
VC1
20
VC2
21
VC3
22
BLK1
23
BLK2
24
BLK3
25
HDOUT
26
VSS
27
VDD(I)
28
CLKOSD
29
AVSS
30
AVDD
31
IREF2
32
CROUT
33 ABAR2
34 COMP2
35 CBOUT
36 VREF2
37 COUT
38 AVDD
39 AVSS
40 IREF1
41 YCOUT
42 ABAR1
43 COMP1
44 YSOUT
45 VREF1
46 AVSS
47 AVDD
48 SCANEN
49
AMUTE
50
HRP1
51
HRP2
52
CSI0
53
CSI1
54
CSI2
55
CSI3
56
ADDATEST
57
VDD(C)
58
VSS
59
YSI0
60
YSI1
61
YSI2
62
YSI3
63
INH
64
INV
C3216
0.01
TL3202
C3718
0.1
R3727
4.7k
R3722
150
R3726
4.7k
R3728
150
R3724
4.7k
R3725
150
C3715
0.01
Q3703
2SA1774/QR/-X
Q3705
PUMT1-W
5
3 6
2
1 4
R3729
OPEN
R3730
OPEN
R3731
OPEN
C3701
10
T
C3205
47/4
_0.5%
_0.5%
_0.5%
_0.5%
_0.5%
_0.5%
_0.5%
_0.5% _0.5%
yf123_y10574001a_rev0.1
MAIN(VIDEO) 1 0
TO PARAGON
TO MAIN IF(CN104),
CPU,PARAGON
TO PARAGON
TO CPU
TO CPU,
PARAGON
TO CPU
TO CPU,OP DRV
TO CPU
TO CPU
TO PARAGON
TO PARAGON,
REG
TO CPU,
PARAGON
TO MAIN IF(CN101)
TO MAIN IF
(CN101,102)
TO MAIN IF(CN101)
TO MONI/VF
TO MAIN IF
(CN103),
MONI/VF
TO MAIN IF
(CN103)
MAIN(VIDEO) SCHEMATIC DIAGRAM
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.