A
1
2
3
4
5
B
C
D
E
F
G
DDR_DQ0 to 15
DDR SDRAM
IC1602
DDR SDRAM section (SHEET 11)
IEEE1394 section (SHEET 10)
IEEE1394
terminal
IEEE1394
controller
IC1801
TPA+ TPA- TPB+ TPB-
PHY_RESET[L]
PHY_LREQ PHY_CLK
PHY_CNA PHY_CTL[0],[1]
PHY_DATA[0-7] PHY_LPS
PHY_LINK_ON
DDR SDRAM
IC1601
RA1613 to
RA1616
RA1609 to
RA1612
RA1625 to
RA1628
R1606 to
R1609
RA1635
R1601 to R1604
RA1634
DDR_DQ16 to 31
SDRAM_DQ16 to 31
SDRAM_A_17
SDRAM_DQ0 to 15
SDRAM_A0 to 15
SDRAM_CKE
SDRAM_RAS_L
SDRAM_CAS_L
SDRAM_WE_L
SDRAM_DQM0 to 3
SDRAM_DQS0 to 3
SDRAM_CLK0,1
SDRAM_CLK_L0,1
DDR_CLK0,1
DDR_CLK_L0,1
DDR_DQM0 to 3
DDR_DQS0 to 3
DDR_CKE
DDR_RAS_L
DDR_CAS_L
DDR_WE_L
DDR_BA0,1
DDR_A0 to 12
CN4104
J4112
CN1801
Media processor (SHEET 12)
Media
processor
IC1401
ATA_DMAACK[L] ATA_INTRQ ATA_ADD0 to 4
ATA_DIOR[L] ATA_DIOW[L] ATA_IORDY
ATA_DAT0 to 15 ATA_RESET ATA_DMARQ
ATA_DMAACK[L] ATA_INTRQ ATA_ADD0 to 4 ATA_DIOR[L]
ATA_DIOW[L] ATA_IORDY ATA_DAT0 to 15 ATA_RESET
ATA_DMARQ
RD/WR[L] ALE OE[L]/LDS[L] MADD1 to 22 CS[0] E5_RESET[L]
AI_SCLK AI_FSYNC AI_MCLKO V_Y_OUT SY_OUT SC_OUT
G_Y_OUT B_PB_OUT R_PR_OUT AO_D_0 AO_SCLK AO_FSYNC
AO_IEC958 AO_MCLK AI_D_0 SPI_CLK A_DAC_CS SPI_MOSI
A_MUTE2_H G_TX G_RX IRTX K_BUS_CLK K_BUS_REQ
SYS_RESET_L K_BUS_OUT K_BUS_IN DAC_RST_L
E5_RESET_L VI_D2 to D9 VIDEO_27M SIO_SCL SIO_SDA
ALE MADD6 to 21
64Mbit Flash
IC1201
MADD1 to 22
IC1202
IC1203
FLASH-ROM section (SHEET 15)
To Front end board
of drive unit
ATAPI Interface section (SHEET 14)
CN2201
Digital junction section (SHEET 16)
K_BUS_CLK K_BUS_REQ K_BUS_IN K_BUS_OUT
TO CN4101
SHEET 7
CN1101
AI_MCLK AI_FSYNC AI_SCLK AI_D[0] DAC_SDA DAC_SCL A_DAC_CS
DAC_RST[L] AO_FSYNC AO_D[0] AO_SCLK AO_IEC958
TO CN4102
SHEET 7
CN1102
C_IN YV_IN
G_Y_OUT B_PB_OUT G_TX IRTX G_RX SYS_RESET[L] A_MUTE[H]
SY_OUT SC_OUT V_Y_OUT R_PR_OUT
TO CN4103
SHEET 7
CN1103
RD/WR[L] E5_RESET[L] OE[L]/LDS[L] CS[0]
LH_AR6 to 22
DIGITAL 5 0
Video decoder section (SHEET 13)
Video
decoder
IC1901
C_IN VY_IN
VI_D2 to D9 VIDEO_27M E5_RESET_L SIO_SCL SIO_SDA
2-7
2-8
