1-36 (No.22036)
4.11 LA72723(IC3): RDS demodulation
• Pin layout
• Block Diagram
• Pin functions
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VREF
MPXIN
Vdda
Vssa
FLOUT
CIN
TES
XOUT
RDS-ID/READY
RDCL
RDDA
RST
MODE
Vddd
Vssd
XIN
Pin No.
Symbol
I/O
Function
1
VREF
O
Reference voltage output (Vdda/2)
2
MPXIN
I
Baseband (multiplexed) signal input
3
Vdda
-
Analog power supply (+5V)
4
Vssa
-
Analog ground
5
FLOUT
O
Subcarrier input (filter output)
6
CIN
I
Subcarrier input (comparator input)
7
TEST
I
Test input
8
XOUT
O
Crystal oscillator output (4.332MHz)
9
XIN
I
Crystal oscillator input (exeternal reference input)
10
Vssd
-
Digtal ground
11
Vddd
-
Digtal power supply
12
MODE
I
Read mode setting (0:master, 1:slave)
13
RST
I
RDS-ID/RAM reset (positive polarity)
14
RDDA
O
RDS data output
15
RDCL
I/O RDS clock output (master mode)/RDS clock input (slave mode)
16
RDS-ID/READY
O
RDS-ID/READY output (negative polarity)
REFERENCE
VOLTAGE
ANTI ALIASING
FILTER
SMOOTHING
FILTER
CLOCK
RECOVERY
(1187.5Hz)
DATA
DECODER
RAM
(128-bits)
RDS-ID
DETECT
57kHz
BPF
(SCF)
+
-
Vddd
Vdda
Vssa
MPXIN
Vssd
RDDA
RDCL
MODE
RST
RDS-ID/
READY
CLK(4.332MHz)
OSC
XIN
XOUT
TEST
TEST
FLOUT
VREF
VREF
CIN
PLL
(57kHz)
+5V
+5V
Summary of Contents for CA-UXP55
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