MX-J270V
1-35
1
2
3
4
5
6
7
8,9
10
11 15
16
17
18
19
20
21
22
23 28
29
30,31
32,33
34 37
38
39 42
43
44
45
46
47
48
49
50
51,52
53 57
58
59 63
64
65
66 72
73
74 76
77
78 80
81
82 84
85
86 89
90
91 94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
HA2
DS
W/R
IRQ
DTACK
HD0
IO VDD
HD1,2
CKT VSS
HD3 7
IOVSS
TEST
XTLVSS
XTLIN
XTLOUT
XTLVDD
CKTVDD
MD0 5
IOVDD
MD6,7
MCE01
MD8 11
IOVSS
MD12 15
5VVDD
LCAS
LCASIN
CKTVSS
MWE
UCAS
IOVDD
UCASIN
RAS0,1
MA9 5
IOVSS
MA4 0
PIO0
IOVDD
VD0 6
IOVSS
VD7 9
CKTVDD
VD10 12
IOVDD
VD13 15
CKTVSS
VD16 19
IOVSS
VD20 23
VSYNC
HSYNC
VOE
VCOVDD
VCLK
VCOVSS
RESET
IOVSS
C2PO
CDLRCK
CDDATA
CDBCK
DALRCK
DADATA
DABCK
IOVDD
XCK
CKTVDD
PIO12
PIO11
PIO10
PIO9
PIO8
PIO7
PIO6
PIO5
PIO4
PIO3
5VVDD
PIO2
IOVSS
PIO1
HA0
HA1
Host address.
Data strobe terminal.
I/O read terminal.
Interact terminal.
Acknowledge data output.
Host data terminal.
Power supply for input/output.
Host data terminal.
Connected to GND.
Date data terminal.
Ground terminal for Input/Output.
Test terminal.
Oscillator ground terminal.
Oscillator input terminal.
Oscillator output terminal.
Power supply for oscillator.
Power supply.
DRAM data / ROM data terminal.
Power supply for Input/Output.
DRAM data/ROM data terminal.
Chip enable output for ROM bank.
DRAM data/ROM data terminal.
Ground terminal for Input/Output.
DRAM data/ROM address terminal.
Power supply (+5V).
DRAM LCAS/ROM address terminal.
DRAM LCAS input.
Connect to GND.
DRAM write enable signal output.
DRAM UCAS/ROM address terminal.
Power supply for Input/Output.
DRAM UCAS input terminal.
DRAM RAS0,1 terminal.
DRAM data/ROM address terminal.
Ground terminal for Input/Output.
DRAM data/ROM address terminal.
ROM address extension terminal.
Power supply for Input/output.
Video data terminal
(R6/CrCb6/YCrCb066)
Ground terminal for Input/Output.
Video data terminal
(R7/CrCb7/YCrCb7)(G0,1/Y0,1)
Power supply.
Video data terminal (G24/Y24)
Power supply for Input/Output.
Video data terminal (G57/Y57)
Connect to GND.
Video data terminal(B0B3)
Ground terminal for Input/Output.
Video data terminal(B47)
Vertical comparator/Composite
comparator output.
Horizontal synchronizing signal.
Video output enable signal.
Power supply of VCO.
Video clock terminal.
Ground of VCO.
Reset signal input.
Ground terminal for Input/Output.
Data error flag input.
L/R word clock input.
Bit serial data input.
Bit clock output.
L/R clock output.
Bit serial PCM audio signal output.
Bit clock output.
Power supply for Input/Output.
Bit clock input terminal.
Power supply.
Interact 2 signal output.
Non connect.
Host enable signal input.
Boot ROM enable signal input.
Non connect.
DAC emphasis signal output.
CD-DA emphasis signal output.
Non connect.
FMV detect signal output.
CD-DA video CD select signal
output Low:Video CD.
Power supply (+5V).
Non connect.
Ground for Input/Output.
Non connect.
Host address input.
Host address input.
I
I
I
O
O
I/O
-
I/O
-
I/O
-
I
I
I
O
-
-
I/O
-
I/O
O
I/O
-
I/O
-
O
I
-
O
O
-
O
O
-
O
O
-
O
-
O
-
O
-
O
-
O
-
O
I/O
I/O
I
-
I/O
-
I
-
I
I
I
I
O
O
O
-
I
-
O
O
I
I
O
O
I
O
O
O
-
O
-
O
-
-
Pin No.
Symbol
I/O
Function
Pin No.
Symbol
I/O
Function
CL480-F1 (IC101) : MPEG-1 Audio / Video decoder
Summary of Contents for CA-MXJ270V
Page 36: ...MX J270V 1 36 HD74HCT244 IC113 Buffer 1 Terminal layout 2 Block diagram ...
Page 43: ...MX J270V 1 43 TC9409BF IC601 KARAOKE DSP ...
Page 58: ...A B C 1 2 3 4 5 MX J270V 2 13 CD Servo control board ...
Page 59: ...A B C D 1 2 3 4 5 MX J270V 2 14 Video CD board ...
Page 60: ...A B C 1 2 3 4 5 MX J270V 2 15 CD Tray section switch board Cam switch board ...
Page 61: ...MX J270V 2 16 MEMO ...