MX-GT700
1-32
LC72131(IC02) : PLL frequency synthesizer for electron alignment
12
10
9
8
7
6
2. Block diagram
5
4
15
19
3
13
CCB
I/F
1
20
16
17
18
11
1
2
Reference
Driver
Swallow
Counter
1/16,1/17 4bits
12bits
Programmable
Divider
Power
on
Reset
Data Shift Register & Latch
Unlock
Detector
Phase
Detector
Charge
Pump
Universal
Counter
1. Pin layout
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
XOUT
VSS
AOUT
AIN
PD
VDD
FMIN
AMIN
I02
IFIN
XIN
CE
DI
CL
DO
BO1
BO2
BO3
BO4
I01
14
2
3.Pin function
Pin No.
1
13
Local
oscillator
signal input
Symbol
Functions
Type
Circuit configuration
AMIN
Xtal OSC
FMIN
14
Serial data input : FMIN is selected when DVS is set to 1.
The input frequency range is from 10 to 160MHz.
The signal is passed through a built-in divide-by-two prescaler
and then supplied to the swallow counter.
A1 though the range of divisor setting is from
272 to 65, 535, the actual divisor is twice the setting since
there is also a built-in divide-by-two prescaler.
XIN
XOUT
20
Crystal resonator connection
(4.5MHz/7.2MHz)
Serial data input : AMIN is selected when DVS is set to 0.
Serial data input : When SNS is set to 1 :
The input frequency range is form 2 to 40MHz
The signal is supplied directly to the swallow counter.
The range of divisor setting is from 272 to
65, 535 and the actual divisor will be the value set.
Serial data input : When SNS is set to 0 :
The input frequency ranges is from 0.5 to 10MHz.
The signal is supplied directly to a 12-bit
programmable divider.
The range of divisor setting is from 4 to 4,095 and the
actual divisor will be the value set.
Local
oscillator
signal input
2
CE
Chip enable
Most be set high when serial data is input to the
LC72131M (DI ), or when serial data is output (DO).
S
(1/2)
