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NJU26207

 

- 7 -

Ver.2008-12-03 

 

Pin setting

 

 

The NJU26207 operates default command setting after resetting the NJU26207. In addition, the NJU26207 

restricts operation at power on by setting PROC pin and MUTEb pin. These pins are input pin. However, these pins 
operate as bi-directional pins. Connect with V

DDIO

 or V

SSIO

 through 3.3k

 resistance. 

 

Table 7   Pin setting 

Pin No. 

Symbol 

Setting 

Function 

“High” 

The NJU26207 operates default setting after reset. 

13 PROC 

“Low” 

The NJU26207 does not operate after reset. Sending start 
command is required for starting operation. 

“High” 

Master volume is set 0dB after reset. 

11 MUTEb 

“Low” 

Master volume is set mute after reset.   

 
 

 

WatchDog Clock

 

 
The NJU26207 outputs clock pulse through WDC (Pin No.12) during normal operation. The WDC clock is useful 

to check the status of the NJU26207 operation. For example, a microcomputer monitors the WDC clock and checks 
the status of the NJU26207. When the WDC clock pulse is lost or not normal clock cycle, the NJU26207 does not 
operate correctly. Then reset the NJU26207 and set up the NJU26207 again. The WDC clock is able to be variable 
for 0msec to 100msec by command. Default setting of WDC clock is 100msec. 

 
The WDC pin is open drain output. The WDC pin setting (Table 8) 

 

Table 8    WDC pin setting 

 
 
 

 
 

Note:

 The cycle of WDC output is rough. Because WDC output inserts in the process of sound processing. 

In slave mode, when there is no input of BCKI/LRI, WDC can’t output. 
It is required to set up a sampling rate correctly. 

 

 
 
 
 

Pin No.  Symbol 

Setting 

WDC pin is used. 

Connect with V

DDIO

 through 3.3k

 resistance. 

12 WDC 

WDC pin is not used. 

Connect with V

SSIO

 through 3.3k

 resistance.   

Do not open WDC pin. 

Summary of Contents for DOLBY NJU26207

Page 1: ...Frequency 32kHz 44 1kHz 48kHz 2 Input channels 2 Output channels Hardware 24bit Fixed point Digital Signal Processing Maximum Clock Frequency 12 288MHz Standard built in PLLCircuit DigitalAudio Inter...

Page 2: ...ALU ALU ADDRESS ADDRESS ADDRESS ADDRESS GENERATION GENERATION GENERATION GENERATION UNIT UNIT UNIT UNIT 24 24 24 24 BIT BIT BIT BIT 24 24 24 24 BIT BIT BIT BIT MULTIPLIER MULTIPLIER MULTIPLIER MULTIPL...

Page 3: ...7 8 9 10 11 12 VDD VSS VSSIO VDDIO SDO0 SDO1 SDO2 TEST SDI3 SDI2 SDI1 SDI0 LRI VDDIO BCKI VSS VDD TEST MUTEb WDC 13 14 15 16 PROC VSSIO VDDIO SEL 36 35 34 33 LRO BCKO MCK VDDIO 17 18 19 20 VDDPLL VSS...

Page 4: ...ply 1 8V 21 CLKOUT O OSC Clock Output 22 CLK I OSC Clock Input 12 288MHz 23 VSSIO I O Power Supply GND 24 VDDIO I O Power Supply 3 3V 25 RESETb I Reset RESETb 0 DSP Reset 26 TEST I for test connect to...

Page 5: ...byte when using either format The SHI operates only in a SLAVE fashion Ahost controller connected to the interface always drives the clock SCL SCK line and initiates data transfers regardless of the...

Page 6: ...byte is shifted into the SDIN pin at the same time that a read byte is shifted out of the SDOUT pin Data transfers are MSB first and are enabled by setting SSb Low Data is clocked into SDIN on rising...

Page 7: ...ing normal operation The WDC clock is useful to check the status of the NJU26207 operation For example a microcomputer monitors the WDC clock and checks the status of the NJU26207 When the WDC clock p...

Page 8: ...libration Level Command 10 Digital Volume Level Command 11 Analog Volume Level Command 12 Reset Flag Command 13 Input Select Delay Command 14 Up data Command 15 Firmware Version Number Request Command...

Page 9: ...Laboratories Please refer to the licensing application manual issued by Dolby Laboratories CAUTION Thespecificationsonthisdatabookareonly givenforinformation withoutanyguarantee asregardseither mista...

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