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3-6-2 AGP Timing Settings
Phoenix – AwardBIOS CMOS Setup Utility
AGP Timing Settings
Item Help
AGP Aperture Size 128M
AGP Transfer Mode 8X
AGP Driving Control Auto
X AGP Driving Value 9A
AGP Fast Write Disabled
AGP Master 1 WS Write Disabled
AGP Master 1 WS Read Disabled
CPU to AGP Post Write Enabled
AGP Delay Transaction Disabled
AGP 3.0 Calibration Cycle Enabled
Menu Level >>
↑↓→←
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
Note: Change these settings only if you are familiar with the chipset.
3-6-3 PCI Timing Settings
Phoenix – AwardBIOS CMOS Setup Utility
PCI Timing Settings
Item Help
PCI Master 1 WS Write Disabled
PCI Master 1 WS Read Disabled
CPU to PCI Post Write Enabled
PCI Delay Transaction Disabled
VLink Data Rate 8X
Menu Level >>
↑↓→←
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
